TMS470MF06607: tms470mf06607 spi chip_selects enabling and disabling

VENKATESH BUGATA

Part Number: TMS470MF06607
Other Parts Discussed in Thread: HALCOGEN

Hi,

i am using the HALCOGEN for generating the spi code for the TMS470MF06607. after generating the code i am using ccs for flashing code into TMS470MF06607 lanchpad.

But am facing the problem with chip-selects, here the chip-selects are enabling and disabling automatically.

i need to know how can i enable and disable the chip-selects when i required.

please help to solve the problem,here i am attaching the code please check it.

**here i enabled spi in master mode.

thanks.

//spi.c

#include "spi.h"

void spiInit(void)
{

sint32 i ;

/** @b initialize @b MIBSPI1 */

/** bring SPI out of reset */
spiREG1->GCR0 = 1U;

/** enable MIBSPI1 multibuffered mode and enable buffer RAM */
spiREG1->MIBSPIE = (spiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U;

/** MIBSPI1 master mode and clock configuration */
spiREG1->GCR1 = (spiREG1->GCR1 & 0xFFFFFFFCU) | ((1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */

/** MIBSPI1 enable pin configuration */
spiREG1->INT0 = (spiREG1->INT0 & 0xFEFFFFFFU) | (0U << 24U); /* ENABLE HIGHZ */

/** - Delays */
spiREG1->DELAY = (2U << 24U) /* C2TDELAY */
| (2U << 16U) /* T2CDELAY */
| (0U << 8U) /* T2EDELAY */
| 0U; /* C2EDELAY */

/** - Data Format 0 */
spiREG1->FMT0 = (2U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 8U; /* data word length */

/** - Data Format 1 */
spiREG1->FMT1 = (2U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 8U; /* data word length */

/** - Data Format 2 */
spiREG1->FMT2 = (2U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 8U; /* data word length */

/** - Data Format 3 */
spiREG1->FMT3 = (2U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 8U; /* data word length */

/** - wait for buffer initialization complete before accessing MibSPI registers */
while ((spiREG1->FLG & 0x01000000U) != 0U)
{
} /* Wait */

/** - initialize transfer groups */
spiREG1->TGCTRL[0U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (0U << 8U); /* start buffer */

spiREG1->TGCTRL[1U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (8U << 8U); /* start buffer */

spiREG1->TGCTRL[2U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[3U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[4U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[5U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[6U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[7U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U) << 8U); /* start buffer */

spiREG1->TGCTRL[8U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8) << 8U); /* start buffer */

spiREG1->TGCTRL[9U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[10U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[11U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[12U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[13U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[14U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0) << 8U); /* start buffer */

spiREG1->TGCTRL[15U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0U+0) << 8U); /* start buffer */

spiREG1->LTGPEND =(spiREG1->LTGPEND & 0xFFFF00FFU) | ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0U+0U+0U)-1U);

/** - initialize buffer ram */
{
i = 0U;
if (8U > 0U)
{
while (i < (8U-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
if (8U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (1U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0 > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+8U+8U+8U+8U+8U+8U+8U+0U+0U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (1U << 12U) /* chip select hold */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM1->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold must be zero for last buffer */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
}

/** - set interrupt levels */
spiREG1->LVL = (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */

/** - clear any pending interrupts */
spiREG1->FLG |= 0xFFFFU;

/** - enable interrupts */
spiREG1->INT0 = (spiREG1->INT0 & 0xFFFF0000U)
| (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */

/** @b initialize @b MIBSPI1 @b Port */

/** - MIBSPI1 Port output values */
spiREG1->PCDOUT = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 4U) /* SCS[4] */
| (1U << 5U) /* SCS[5] */
| (1U << 6U) /* SCS[6] */
| (1U << 7U) /* SCS[7] */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */

/** - MIBSPI1 Port direction */
spiREG1->PCDIR = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (0U << 4U) /* SCS[4] */
| (1U << 5U) /* SCS[5] */
| (1U << 6U) /* SCS[6] */
| (0U << 7U) /* SCS[7] */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */

/** - MIBSPI1 Port open drain enable */
spiREG1->PCPDR = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 4U) /* SCS[4] */
| (0U << 5U) /* SCS[5] */
| (0U << 6U) /* SCS[6] */
| (0U << 7U) /* SCS[7] */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */

/** - MIBSPI1 Port pullup / pulldown selection */
spiREG1->PCPSL = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 4U) /* SCS[4] */
| (1U << 5U) /* SCS[5] */
| (1U << 6U) /* SCS[6] */
| (1U << 7U) /* SCS[7] */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */

/** - MIBSPI1 Port pullup / pulldown enable*/
spiREG1->PCDIS = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 4U) /* SCS[4] */
| (0U << 5U) /* SCS[5] */
| (0U << 6U) /* SCS[6] */
| (0U << 7U) /* SCS[7] */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */

/* MIBSPI1 set all pins to functional */
spiREG1->PCFUN = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 4U) /* SCS[4] */
| (1U << 5U) /* SCS[5] */
| (1U << 6U) /* SCS[6] */
| (1U << 7U) /* SCS[7] */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */

/** - Finally start MIBSPI1 */
spiREG1->GCR1 = (spiREG1->GCR1 & 0xFEFFFFFFU) | (1U << 24U);

}

void spiSetData(spiBASE_t *spi, uint32 group, uint16 * data)
{
spiRAM_t *ram = spi == spiREG1 ? spiRAM1 : spiRAM2;
uint32 start = (spi->TGCTRL[group] >> 8U) & 0xFFU;
uint32 end = group == 7U ? (((spi->LTGPEND & 0x0000EF00U) >> 8U) + 1U) : ((spi->TGCTRL[group+1U] >> 8U) & 0xFFU);

if (end < start) {end = 128U;}

while (start < end)
{
ram->tx[start].data = *data++;
start++;
}
/* USER CODE BEGIN (0) */
/* USER CODE END */
}

void spiEnableGroupNotification(spiBASE_t *spi, uint32 group, uint32 level)
{
if (level != 0U)
{
spi->TGITLVST = (spi->TGITLVST & 0x0000FFFFU) | ((1U << group) << 16U);
}
else
{
spi->TGITLVCR = (spi->TGITLVCR & 0x0000FFFFU) | ((1U << group) << 16U);
}
spi->TGITENST = (spi->TGITENST & 0x0000FFFFU) | ((1U << group) << 16U);
}

void spiTransfer(spiBASE_t *spi, uint32 group)
{
spi->TGCTRL[group] |= 0x80000000U;
}

int main()
{
rtiInit();
spiInit();
gioInit();
hetInit();
gioSetDirection(gioPORTA,0xFFFFFFFF);
gioSetDirection(hetPORT,0xFFFFFFFF);
rtiEnableNotification(rtiNOTIFICATION_COMPARE0);
//_enable_IRQ();
rtiStartCounter(rtiCOUNTER_BLOCK0);
Edge = LOW;

//spiEnableGroupNotification(spiREG1,0,0);
spiEnableGroupNotification(spiREG1,0,0);
spiEnableGroupNotification(spiREG1,1,0);
spiEnableGroupNotification(spiREG1,2,0);
spiEnableGroupNotification(spiREG1,3,0);
spiEnableGroupNotification(spiREG1,4,0);
spiEnableGroupNotification(spiREG1,5,0);
spiEnableGroupNotification(spiREG1,6,0);
spiEnableGroupNotification(spiREG1,7,0);
spiSetData(spiREG1,0,TG0_TX_DATA);
spiSetData(spiREG1,1,TG0_TX_DATA);
spiSetData(spiREG1,2,TG0_TX_DATA);
spiSetData(spiREG1,3,TG0_TX_DATA);
spiSetData(spiREG1,4,TG0_TX_DATA);
spiSetData(spiREG1,5,TG0_TX_DATA);
spiSetData(spiREG1,6,TG0_TX_DATA);
spiSetData(spiREG1,7,TG0_TX_DATA);
while(1)
{
spiTransfer(spiREG1,0);
spiTransfer(spiREG1,1);
spiTransfer(spiREG1,2);
spiTransfer(spiREG1,3);
spiTransfer(spiREG1,4);
spiTransfer(spiREG1,5);
spiTransfer(spiREG1,6);
spiTransfer(spiREG1,7);

}

over 6 years ago

0 QJ Wang over 6 years ago

TI__Guru**** 186196 points

Hello,

During the SPI transmission, the value of the chip select control field CSNR[7:0] of the SPIDAT1 register is driven on SPI_CS pins. When the transmission finishes the default CS value (defined by the CSDEF register) is put on the SPI_CS pins.

If you want to manually control the chip select of your slave devices, you can configure the CS pin as GIO, then set and clear this pin manually.

0 VENKATESH BUGATA over 6 years ago in reply to QJ Wang

Prodigy 85 points

hi QJ Wang,
i have tried like that means i have configured a GIO4 for chip select but that data is not sending to the slave.

i have used arduino uno board as a slave, communicating the tms470mf06607(master) and arduino uno (slave).
in this case master side GIO4 enabled and spi1 enabled, that GIO4 connected to the chip select of that arduino uno, but the data is not sending.
i am adding that main functions of arduino uno and tms470 main functions, please find the problem where it is

thanks advance

//tms470 master

while(1)
{
gioSetBit(gioPORTA,4,1);
//// spiREG1->PCSET = ((spiREG1->PCSET) & 0xFFFFFFFF);// 1U;
//
// // spiREG1->PCSET = ((spiREG1->PCSET) | 2U);//1U
spiTransfer(spiREG1,0);
// // spiREG1->PCCLR = ((spiREG1->PCCLR) | 2U);// 0U;
//
// //spiREG1->PCSET = ((spiREG1->PCSET) & 0xFFFFFFFE);// 1U;
//// gioSetBit(spiREG1->PCSET,0,1);
gioSetBit(gioPORTA,4,0);
}

#include <SPI.h>
#define BUFF_LEN 8
byte buff[BUFF_LEN];
byte Buff[BUFF_LEN]{9,8,7,6,5,4,3,2};
volatile int pos = 0;
volatile boolean process_it = false;
int num = 0;
//PIN 13 --> SCK
//PIN 12 --> MISO
//PIN 11 --> MOSI
//PIN 10 --> SS

void setup()
{
////set CS direction
//
//pinMode(CS, OUTPUT);
////initialize SPI
//SPI.begin();

Serial.begin(9600);
Serial.println("spi test");
pinMode(MISO, OUTPUT);
digitalWrite(MISO , LOW);

//SPCR IS A SPI CONTROL REGISTER
SPCR |= _BV(SPE);//SPE --> SPI ENABLE
SPCR |= _BV(SPIE);//SPIE --> SPI INTERRUPT ENABLE //SPI.attachInterrupt();
}
//ISP --> INTERRUPT SERVICE ROUTINE
//SPI_STC_vect --> SPI TRANSFER COMPLETE VECTOR INTERRUPT
ISR(SPI_STC_vect)
{
byte c = SPDR;//SPI DATA REGISTER
if(pos < sizeof( buff))
{
buff[pos++] = c;
//Serial.println("buff["+ String(pos)+"]:" + String(buff[pos]) + ".");
if(c == 1)
{
process_it = true;
}
}

}
void loop()
{

if(process_it)
{
for(int i=0;i<pos;i++)
{
Serial.println("buff["+ String(i)+"]:" + String(buff[i]) + ".");
}
Serial.println("printed the data" + String(num++));

pos = 0;
process_it = false;
}
}

0 QJ Wang over 6 years ago in reply to VENKATESH BUGATA

TI__Guru**** 186196 points

Here, I wrote an example for your reference:

/* Enable/Disable SPI Chip Select */
void SPI_ssel (unsigned long ssel) {
if (ssel) {
spiREG1->PCDOUT |= 0x01; // CS[0] = high; CS[0] pin is configured as GIO
} else {
spiREG1->PCDOUT &= ~0x01; // CS[0] = low
}
}

/* Write and Read a byte on SPI interface */
unsigned char SPI_send (unsigned char outb) {
while ((spiREG1->FLG & 0x0200) == 0); // Wait until TXINTFLG is set for previous transmission
spiREG1->DAT1 = outb | 0x100D0000; // transmit register address

while ((spiREG1->FLG & 0x0100) == 0); // Wait until RXINTFLG is set when new value is received
return((unsigned char)spiREG1->BUF); // Return received value
}

0 VENKATESH BUGATA over 6 years ago in reply to QJ Wang

Prodigy 85 points

Hi QJ Wang

there is no use of the above example, i have tried that one but nothing is transmitting and chip select is not toggling.

thank you.

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS470MF06607: tms470mf06607 spi chip_selects enabling and disabling