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F05 Flash API timing parameter question

Other Parts Discussed in Thread: TMS470R1B768


I'm writing a bootloader program for TMS470R1B768, using F05 Flash API to erase and program flash.

After reading SPNU257, I am a little confused about the "Flash Delay Parameter Values".

In the user's specification, a table is provided to determine the Flash Delay Parameter based on "Frequency". My question is what is this frequency, is it SYSCLK or ICLK or something else?

If this is the SYSCLK, is it right that the F05 Flash API support a maximum frequency of 24MHz. Can I erase or program under a higher SYSCLK frequency (like 48MHz).

Thanks in advance.

  • Hello Yang

    Please be aware that the TMS470R1 Series (including the TMS470R1B768 device) is not recommended for new designs. However, the device, tool, or software continues to be in production to support existing customers.  Please see the full 'NRDN' notice here.

    Soon TI will be launching the new TMS470M series of microcontrollers.  This series will feature greater ARM CPU performance and a similar peripherial set to the TMS470R1 Series of microcontrollers.  Please come back soon for more information about the TMS470M Series of microcontrollers.  The product preview for the first two microcontrollers in the TMS470M series is available here: TMS470MF0660x - SPNS157.

    Now to your question.  This parameter is based off of the System Frequency.  The max System Frequency for Flash operations is 24MHz and must be in non-pipelined mode.