RM48L530: pin status after reset

in the technical refrence manual there are information about status of pins after reset. But they are a little bis confusing for me.
* GIO Data Direction Registers (GIODIR[A-B]).
It is always 0 after reset means, that it is always input and output buffer is tristated.
* GIO Data Output Registers (GIODOUT[A-B]).
The pin is driven to logic low (0) after reset.
For me it is a little bit contradictory. Either it is input and output buffer is in tristate or it is driven low.
Where is my problem in understanding the right state of GPIOs after reset?
I need help!

Hi Winfried,

All I/O terminals (except for nRST) are configured as inputs during power-on-reset active and immediately after power-on-reset is released until the time when system reset (nRST) is released. These terminals are pulled down or high depending on the default function on each terminal. For example, all terminals with default GIO signals are configured as inputs and pulled down internally during this reset phase. Once the system reset is released, the I/Os are controlled by the default states of the individual control registers. For example, the GIODIRx register defaults to configuring all GIOx terminals as inputs (DIR = 0). In this case the value of the DOUT, DSET and DCLR registers do not affect the terminals. The pull select registers (PULSEL) define the pull applied to the terminals. In case of GIOx terminals, the pull-select registers default to applying a pull-down on the terminals.

See also my comments embedded in the message below:

ECLK (in standard operation we generate 1MHz clock for external cuicuit through this pin). Should be off (high or low, but no clock) after reset and only active after restart in software, because after reset it should be in safe mode without clock.

>> ECLK is off by default. It is an input pin and it is pulled down (low). Software must program the functionality of this pin to output a clock signal.

GIOA[0] ... GIOA[6]: are they in tri state after reset (nRST was driven low) or driven low? I want to connect relais drivers which shlould be off after reset (safe state).

>> GIOx are pulled down when nRST is active. This is a weak pull (20uA) and can be overridden externally if you so wish.

In datasheet there is any nformation about registers but I don't know if the value of a register is the same value as the state of the pin.

>> Yes, the default pull states of the pins have been chosen to match the pull-select registers for I/O pins.

* GIO Data Direction Registers (GIODIR[A-B]).
It is always 0 after reset means, that it is always input and output buffer is tristated.

>> Yes, this is correct. The PSEL (pull-select) and PDIS (pull-disable) registers define the pull applied to these pins.

* GIO Data Output Registers (GIODOUT[A-B]).
The pin is driven to logic low (0) after reset.
For me it is a little bit contradictory. Either it is input and output buffer is in tristate or it is driven low.
Where is my problem in understanding the right state of GPIOs after reset?

>> The DOUT, DSET and DCLR registers do not affect the pin state until the pin is configured as an output pin.