Other Parts Discussed in Thread: TMS570LS20216
Device: RM48L530
IDE: IAR 8.11.3.13984
Compiler: IAR 8.11.3.13950
OS: Sciopta 1.9.15.10
Hi,
I'm trying to implement a fault insertion test for RAM ECC on the RM48 and have modeled my solution after one provided for the TMS570LS20216. When reading back tcram1bit, RAMOCCUR is not incremented, and so no error handling occurs. I've added my implementation below. Would someone please explain this behavior? Thank you.
#ifndef __FI_RAM_ECC_CHECK_H__ #define __FI_RAM_ECC_CHECK_H__ #include <stdint.h> #ifdef __cplusplus extern "C" { #endif #define tcram1REG ((tcramBASE_t *)(0xFFFFF800U)) #define tcram2REG ((tcramBASE_t *)(0xFFFFF900U)) #define tcram1bit (*(unsigned int *)0x08000000) #define tcram2bit (*(unsigned int *)0x08000008) #define tcram1bitError (*(unsigned int *)0x08400000) #define tcram2bitError (*(unsigned int *)0x08400008) #define TCRAM_RAMCTRL_ECCWREN (uint32_t)(1u << 8u) /* Tcram Register Frame Definition */ /** @struct tcramBase * @brief TCRAM Wrapper Register Frame Definition * * This type is used to access the TCRAM Wrapper Registers. */ /** @typedef tcramBASE_t * @brief TCRAM Wrapper Register Frame Type Definition * * This type is used to access the TCRAM Wrapper Registers. */ typedef volatile struct tcramBase { uint32_t RAMCTRL; /* 0x0000 */ uint32_t RAMTHRESHOLD; /* 0x0004 */ uint32_t RAMOCCUR; /* 0x0008 */ uint32_t RAMINTCTRL; /* 0x000C */ uint32_t RAMERRSTATUS; /* 0x0010 */ uint32_t RAMSERRADDR; /* 0x0014 */ uint32_t rsvd1; /* 0x0018 */ uint32_t RAMUERRADDR; /* 0x001C */ uint32_t rsvd2[4U]; /* 0x0020 */ uint32_t RAMTEST; /* 0x0030 */ uint32_t rsvd3; /* 0x0034 */ uint32_t RAMADDRDECVECT; /* 0x0038 */ uint32_t RAMPERADDR; /* 0x003C */ } tcramBASE_t; typedef enum { CORRECT, DETECT } ECCAction; void FI_CheckRAMECC(ECCAction testType); #endif #ifdef __cplusplus } #endif
#include "ram_ecc_check.h" #include "flexconn_interface.h" void FI_CheckRAMECC(ECCAction testType) { volatile uint64_t u64_RamRead = 0; /* Read-unlock the error addresses for subsequent captures */ u64_RamRead = tcram1REG->RAMUERRADDR; u64_RamRead = tcram2REG->RAMUERRADDR; /* Enable Writes to ECC RAM */ (tcram1REG->RAMCTRL) |= (TCRAM_RAMCTRL_ECCWREN); (tcram2REG->RAMCTRL) |= (TCRAM_RAMCTRL_ECCWREN); switch(testType) { case CORRECT: /* Clear RAMOCCUR before setting value */ tcram1REG->RAMOCCUR=0u; tcram2REG->RAMOCCUR=0u; /* Set RAMTHRESHOLD to 1 */ tcram1REG->RAMTHRESHOLD = 1u; tcram2REG->RAMTHRESHOLD = 1u; /* Allow error to be reported to ESM */ tcram1REG->RAMINTCTRL = 0x01; tcram2REG->RAMINTCTRL = 0x01; /* cause a 1-bit ECC error */ tcram1bitError ^= 0x01; /* Restore ctrl registers */ tcram1REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN; tcram2REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN; /* read from corresponding RAM location */ u64_RamRead = tcram1bit; /* check that error registered */ if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) { FC_ErrorHandler(RAM_ERROR); } else { tcram1REG->RAMERRSTATUS = 0x1; // clear SERR flag tcram2REG->RAMERRSTATUS = 0x1; } break; case DETECT: /* cause a 2-bit ECC error */ tcram2bitError ^= 0x03; /* Restore ctrl registers */ tcram1REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN; tcram2REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN; /* read from corresponding RAM location */ u64_RamRead = tcram2bit; break; default: break; } }