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ADC issues

Guru 54027 points
Part Number: EK-TM4C1294XL
Other Parts Discussed in Thread: INA240, LM3S8971

ADC0 30mHz ADCCLK, 2MSPS, SS2, no hardware averaging, TSHN encoding 0x0000.

Yet another odd behavior analog periodic signal is requiring 500-600us settling time or converter completely misses any and all acquisitions. The odder part is the +VREFP-VREFN (Fig 15-9) mv per ADC code precision is no were close to 802uV let alone even 10mV. CADC charge sharing on AINx channels from a digital converter perspective is being held charge states from SW side of equation. Processed FIFO values are mostly based on mathematical non-sense according to CCS register debug results. CCS 7.3 register debug of ADC0 ADCSSFSTATn does not properly indicate HPTR/TPTR movement when processed data proves they should be moving. The FIFO results data remains extremely low, under 0x14 LSB with >100mV periodic AINx analog signals. That alone seems to contradict (Fig 15-9) under these specific hardware conditions.     

Above are the noted symptoms (perceived) very poor ADC performance for a PWM 80us periodic analog signal source. What in firmware could be leading to such very low ADC acquisition precision below 100mv?

Why is the ICDI not sowing any FIFO values via fastest 100ms refresh intervals when the conversion interrupt is being triggered via GPTM oneshot timer in 500-600us intervals? Yet a GUI scope widget is reporting the sequencer has produced sample acquisitions in those 500-600us intervals. How are we supposed to trouble shoot firmware issues when the ICDI revision 12630 fails to properly report register activity? Are these ICDI debug issues fixed in a later revision flash programmer Build >1613?  How would anyone even know what is going on when CCS debug can not give a clear analysis of the conditions?  

Adding any external capacitance on AINx creates excessive open loop gain error above INA240 1nf maximum output loading.  Setting TSHN encoding >0x000 introduces excessive open loop gain errors in FIFO results data >500mV acquisitions. These are typical current measures not rocket science so there a reason the TM4C ADC is producing very crude periodic analog acquisitions. What are the TM4C1294 MIN/MAX specifications for any analog signal acquisition settling and hold times?  

Is it possible AINx input SNRs/SNDRs >72db Nom. is causing mayhem and why would any TI SAR compatible device not have stated conformance measures if that being case? How would any typical customer have the ability to even measure these kind of levels listed in the TM4C electrical specifications? Past Stellaris employees did HW/SW workarounds LM3S8971 ADC using FAN4174IP5X OPAMP to measure PWM periodic current, late discovering even more jaded in error. How they ever made simple OPAMP work when the INA240 embedded with PWM filters on the front end when 240 struggles with TM4C1294 ADC is simply baffling.

  • Hi BP101,

    1. Do you see the same issue you describe on your LP board?
    2. Relying on CCS refresh to display the updated register is not a good idea. I will suggest you output the value via UARTprintf.
    3. With all the problems you are facing so far, have you even tried to add a Op-amps between your signal source and the AINx input.
  • Hi Charles,

    1. This is the EVM or custom doing very same thing.

    2. Yet SS1 via PMW0 trigger conversion every 40us is moving TPTR/HPTR and FIFO data required to debug ADC issues. Perhaps this is an ICDI speed or LMF version update fix issue? The SS2 FIFO data, GPTM oneshot 500us intervals is being output to USB0 bulk device client, the confusing part.

    When reducing GPTM oneshot period the AD converter does not produce useable FIFO values. The idea is to track analog falling edge events. Sadly the GPTM clock source drifts to rising PWM duty cycles, not always exactly 500us. Some how PWMCLK/DIV2 is not keeping synchronous to SYSCLK as the PWM duty changes. Results in acquisition position drift of the falling analog slopes. Such drifting causes wild current swings in the samples until steady state speed is reached. I've witnessed on the scope the two clock sources drifting apart in the PWM duty updates, eventually clocks align to 500us in preset 80-40us PWM periods. The number of PWM synchronous updates does not stop duty drifting, Ralph past noted as being updates related.

    3. The INA240 is an low noise low drift differential amplifier designed specifically to interface directly to SAR ADC. Adding another OPAMP is not the WA we seek.

    Since so much CADC setting (500us) is being required, more recently wondering how to better track analog slope movements?
  • It would seem the ADC trigger GPTM oneshot set for 500-600us converter settling was a bit high and 400us produced less issue at lower MV scale, under 1 amp with lower scale error. The min max sample values went flat line after peak acquisitions, 0-700mA curve quickly bounced up/down ending near 200-300mA.

    Very small loading has roughly 7% error according to the newer INA240 error tool found on product web page. The 400us originally not so good on the higher scale until (float) was added yesterday into current and RMS equations. The initial RMS equation was crude, produced current values no where near 0.707 peak. The odd part is TI had originally used PWM0 triggers in the commutation period, though current seems to be slower than the faster PWM period (80us). Slower current might explain the much longer 400us ADC trigger periods?

    Like for forum to confirm a faster JTAG device (XDS200) will produce faster and moving CCS debug register results?
  • Hi Charles,

    My claim is not without merit (below) Piccolo ADC configuration seems to settle near 2.5us after some how shifting ADC trigger 2 SYSCLKS 12.5ns (80mHz).  The problem TM4C1294 60Mhz PWMCLK with 2.5us blanking delay to trigger conversion window seems to miss any and all sample acquisitions. Our original blanking time was 2.5us but discovered ADC was not producing correct measures. The INA240 propagation delay is not 400us so it should not require such huge time delay! This issue occurs even at 24vdc with very small motor current measures, < 1.5 amp.

    Why does it require 400-500us settling time when typical 12 bit SAR requires typically 600ns to (1/2 LSB) resolution with no added C external? Somehow the ADC clock skews far from SYSCLK time domain and (PWM_TR_CNT_LOAD) fails to trigger ADC conversions center of PWM periods. Configuring SYSCLK 60mHz does not correct ADC skew issue that occurs during 40-80us PWM periods. The industry accepted practice does not produce useable nor correct results nor does 2.5us blanking trigger delay after any PWMENABEL register inverter drive event. There has to be an underlying timing issue PLL 480mHz and 30mHz ADCCLK are not synchronous as it relates SYSCLK(120mHz) with PWMCLK/DIV2 (60mHz). The question is how could our clock configuration cause this issue? Missing any clock inputs datasheet block diagrams makes for difficult analysis. How does TI expect anyone on earth to trouble shoot this seemingly bizarre clocking issue from the main clock tree diagram alone?