Other Parts Discussed in Thread: INA240, LM3S8971
ADC0 30mHz ADCCLK, 2MSPS, SS2, no hardware averaging, TSHN encoding 0x0000.
Yet another odd behavior analog periodic signal is requiring 500-600us settling time or converter completely misses any and all acquisitions. The odder part is the +VREFP-VREFN (Fig 15-9) mv per ADC code precision is no were close to 802uV let alone even 10mV. CADC charge sharing on AINx channels from a digital converter perspective is being held charge states from SW side of equation. Processed FIFO values are mostly based on mathematical non-sense according to CCS register debug results. CCS 7.3 register debug of ADC0 ADCSSFSTATn does not properly indicate HPTR/TPTR movement when processed data proves they should be moving. The FIFO results data remains extremely low, under 0x14 LSB with >100mV periodic AINx analog signals. That alone seems to contradict (Fig 15-9) under these specific hardware conditions.
Above are the noted symptoms (perceived) very poor ADC performance for a PWM 80us periodic analog signal source. What in firmware could be leading to such very low ADC acquisition precision below 100mv?
Why is the ICDI not sowing any FIFO values via fastest 100ms refresh intervals when the conversion interrupt is being triggered via GPTM oneshot timer in 500-600us intervals? Yet a GUI scope widget is reporting the sequencer has produced sample acquisitions in those 500-600us intervals. How are we supposed to trouble shoot firmware issues when the ICDI revision 12630 fails to properly report register activity? Are these ICDI debug issues fixed in a later revision flash programmer Build >1613? How would anyone even know what is going on when CCS debug can not give a clear analysis of the conditions?
Adding any external capacitance on AINx creates excessive open loop gain error above INA240 1nf maximum output loading. Setting TSHN encoding >0x000 introduces excessive open loop gain errors in FIFO results data >500mV acquisitions. These are typical current measures not rocket science so there a reason the TM4C ADC is producing very crude periodic analog acquisitions. What are the TM4C1294 MIN/MAX specifications for any analog signal acquisition settling and hold times?
Is it possible AINx input SNRs/SNDRs >72db Nom. is causing mayhem and why would any TI SAR compatible device not have stated conformance measures if that being case? How would any typical customer have the ability to even measure these kind of levels listed in the TM4C electrical specifications? Past Stellaris employees did HW/SW workarounds LM3S8971 ADC using FAN4174IP5X OPAMP to measure PWM periodic current, late discovering even more jaded in error. How they ever made simple OPAMP work when the INA240 embedded with PWM filters on the front end when 240 struggles with TM4C1294 ADC is simply baffling.