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CC430F5135: The question of BOR

Part Number: CC430F5135

Hi Champs,

According to PMM block diagram of CC430 user's guide below, there is a BOR logic and user's guide tells us during operation, the BOR also generates a reset if VCORE falls below a preset threshold.

If we refer to chapter 1(system control module) and it says 

A BOR is a device reset. A BOR is only generated by the following events:
• Powering up the device
• A low signal on RST/NMI pin when configured in the reset mode
• A wakeup event from LPMx.5 (LPM3.5 or LPM4.5) modes
• A software BOR event

I wonder which one is for real? Will the BOR logic in PMM issues a BOR when VCORE falls below a preset threshold? How can we do to preset the threshold of BOR logic here please?

Please advise if any idea, thanks.

BR,

Luke

  • Luke Chen said:
    How can we do to preset the threshold of BOR logic here please?

    The CC430F5135 datasheet SLAS554I has the following table which gives the threshold at which BOR is asserted / de-asserted:

    Where the above datasheet "PMM Brownout Reset (BOR)" is specified based upon the DVCC input voltage to the PMM, rather than the VCORE output voltage as shown in the CC430 user's guide Figure 2-2. PMM Block Diagram.

    Therefore, there may be an error in the CC430 user's guide, where the BOR monitor should be shown as monitoring the DVCC input voltage to the PMM.

  • Luke,
    As Chester pointed out, the BOR voltage thresholds are specified in section 5.19 of the Datasheet. Although, BOR is not finely tuned and can vary from device to device. Does this address your question?

    Chester,
    I don't think there is an error in the datasheet. I believe the BOR circuitry is actually monitoring the Vcore side of the regular. There will be a relationship of Vcore directly to DVcc. At a minimum, Vcore = DVcc - LDO dropout. So if DVcc drops, BOR can still be spec'd to it vs Vcore.

    Thanks,
    JD
  • Hi JD / Chester,

    I ask this question because my customer uses this device for years and is facing a system problem recently.
    They analysis and find that their hardware discharge slow when system power is removed, CC430F5135 will issue I2C write commands sometimes when DVCC close to 1.5V and this cause their system problem. Sounds like program counter crashes and CPU jumps and executes certain code when DVCC is around 1.5V, is it possible?

    Of course, 1.5V DVCC is out of our spec. But from cusomter's view, they use same part number and software in production for at least 2 years, everything goes well before this issue happen, so they want to know if we have a new revision silicon RTM in past one year. Do you have the information of latest silicon revision number and the RTM date?

    I don't get enough information of BOR, POR and PUC in user's guide, what is the behavior difference between them? for example, clear RAM, set I/O to default state, etc. Do you have this kind of information please?

    Thanks for your support.
    Luke
  • Hey Luke,

    BOR, POR, and PUC's behavior is fully defined in the User's Guide, sections 1.2-1.4. www.ti.com/.../slau259e.pdf I didn't find any new silicon revisions in the last several years. They can check the markings on their devices, and make sure they are all Rev E.

    To address your question, if DVCC is ramping down very slowly it is possible for them to run out of spec like you suggest before BOR puts the defice in reset. This BOR can very from device to device and lot to lot, and we've only specified a max voltage level of 1.45V above.

    In this case, I think the customer should implement a software update and use the SVS to monitor the voltage and hold the device in reset when the DVCC falls below a programmed threshold. Sections 2.2.2 of the above family user's guide and in the block diagram you included in your original question.

    Thanks,
    JD
  • Hi JD,

    My customer uses the SVS to monitor the DVCC voltage and issues a software BOR when DVCC falls below around 1.83V, but this problem is still there, CC430F5135 issues one I2C write command sometimes when DVCC is around 1.5V.

    This means that a software BOR can reset MCU but cannot hold the device in reset, right? As you mentioned, please advise how can we hold the device in reset when DVCC falls below a programmed threshold?

    Thanks for your support.
    Luke
  • Hey Luke,

    The SVS is a complicated module, but it’s performance and behavior is described in section 2.2 of the Family User’s Guide: http://www.ti.com/lit/ug/slau259e/slau259e.pdf

     

    As seen below, when either DVcc or Vcore fall below the SVSx_IT levels, the device will be held in reset until the voltage is brought back above a threshold.  These thresholds can be programmed in the SVS with the SVSLRVL bits.      

    I also looked quickly through the errata, and I didn’t see any that seems to explained the customer’s issue.  My best guess is that this might be an issue with how the SVS is configured or maybe there is a lot of noise on the VCC lines.

    Thanks,

    JD