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TM4C123BH6ZRB: [TM4C123BH6ZRB]Copy buffer inside the EEPROM

yihe
Guru 58090 points

Part Number: TM4C123BH6ZRB

Hello

In the TM4C123BH6ZRB, it mentions that a copy buffer. the copy buffer is only used when a main block is full. My question is how big is the copy buffer? how can a application know that the copy buffer is full?

In the EEPROM Characteristics,

The normal time to program 32 is 110us,  but it is 30ms if a buffer is needed with available space. it is 60ms if a buffer is needed and required erase.

It seems that the time to erase a buffer is the same as erase main block. Does buffer have 7 block size which is 7x16Word?

many thanks

Yihe

  • 0
    TI__Guru*** 128255 points

    Hello Yihe,

    See the following passages:

    The copy buffer is only used when a main block is full because a word has been written seven times and there is no more room to store its latest version. In this situation, the latest versions of all the words in the block are copied to the copy buffer, allowing the main block to be erased safely, providing power down safety. If the copy buffer itself is full, then it must first be erased, which adds extra time.

    Based on this it sounds like it has 7 block size of space in the copy buffer, so I agree with that assessment though I would say the above passage indicates it clearly vs the guess due to time. See: https://e2e.ti.com/support/microcontrollers/other/f/908/p/833412/3083777#3083777

    And this regarding how to know when to erase:

    Register 19: EEPROM Support Control and Status (EESUPP)

    The EREQ bit is set if the internal copy buffer must be erased the next time it is used because it is full. To avoid the delay of waiting for the copy buffer to be erased on the next write, it can be erased manually using this register by setting the START bit.

  • 0 in reply to Ralph Jacobi
    TI__Guru 58090 points

    Hello Ralph

    Thanks

    Mem#1 and 10 in the below errata indicates that START bit shall not be used if PRETRY and ERETRY.

    http://www.ti.com/lit/er/spmz849f/spmz849f.pdf

    Does this impact the EREQ bit?

    Thanks

    Yihe

  • 0 in reply to yihe
    TI__Guru*** 128255 points

    Hello Yihe,

    No these errata items do not impact the EREQ bit. The issues are centered on error recovery for EEPROM. But when using the start bit with EREQ, all it is doing is erasing the copy buffer which is a standard operation rather than trying to recover from errors.

  • 0 in reply to Ralph Jacobi
    TI__Guru 58090 points

    Hello Ralph

    Thanks. in the data sheet, it has block, page, sector, buffer in different location and i am little confused by all these terms.

    The block is 16 words. a sector contains two blocks =32 words. But actually a block is 7 copy, but application only see 16 word 

    what does sector do here?

    what is the page?  At the page 536 of the data sheet(theory of operation)

    it mentioned that when a page runs out of room, a copy buffer is used.

    Is page a block or sector? is the size of copy buffer equal to 7x16word or 7x32x16word?

    the other question is that, does the copy buffer share among 2K eeprom space?

    Could you help me understand this internal mechanism of copy  buffer better?

    Many Thanks

    Yihe 

  • 0 in reply to yihe
    TI__Guru*** 128255 points

    Hello Yihe,

    Each page is 16 words. A 2 page block is 32 words and matches the sector size of the underlying flash which emulates EEPROM.

    I found an E2E post that goes in great detail about the copy buffer: 

    I think that will answer many questions. Also it looks like the copy buffer is only 16 words. There is no 7x depth to it. It just copies the latest version of each of the 16 words to then write after a block erase.

    That post has a ton of detail that even I wasn't fully aware of it, so please give it a thorough read and let me know if you have any doubts.