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CCS/TM4C1290NCZAD: TM4C1290NCZAD

Part Number: TM4C1290NCZAD

Tool/software: Code Composer Studio

The sampling frequency measurement is limited to 1 MHz

I want to raise the sampling frequency to 2 MHz

I tried the command

ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 1);

But I got an error that the compiler does not recognize the function

I checked the ADC.C file and there is no such function

I’m using SW-DK-TM4C129X-2.0.1.11577.exe

It appears in the user manual but not ADC.C !!!

 

I try to implement it by

GetSysCtlClockFreq_var= SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), SYS_CLK_FREQ);

HWREG(ADC0_BASE + ADC_O_PC) |= 0x7;//Full conversion rate

HWREG(ADC0_BASE + ADC_O_CC) =1;

Bat the sampling frequency still limited to 1 MHz

Thanks

Haim 

  • Hi Haim,

    haim rozenboim said:

    I tried the command

    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 1);

    But I got an error that the compiler does not recognize the function

    I checked the ADC.C file and there is no such function

    I’m using SW-DK-TM4C129X-2.0.1.11577.exe

    It appears in the user manual but not ADC.C !!!

    Can you please download the latest TivaWare version 2.1.4.178 and try again? You will also find this post helpful. https://e2e.ti.com/support/microcontrollers/other/f/908/p/690227/2545036#2545036

    //*****************************************************************************
    //
    //! Sets the clock configuration for the ADC.
    //!
    //! \param ui32Base is the base address of the ADC to configure, which must
    //! always be \b ADC0_BASE.
    //! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and
    //! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input.
    //! \param ui32ClockDiv is the input clock divider for the clock selected by
    //! the \b ADC_CLOCK_SRC value.
    //!
    //! This function is used to configure the input clock to the ADC modules.  The
    //! clock configuration is shared across ADC units so \e ui32Base must
    //! always be \b ADC0_BASE.  The \e ui32Config value is logical OR of one
    //! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined
    //! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC.
    //! Not all values are available on all devices so check the device data sheet
    //! to determine value configuration options.  Regardless of the source, the
    //! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts
    //! after dividing must be between 16 and 32 MHz.
    //!
    //! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as
    //! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified.  If the PLL is
    //! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC
    //! is specified.
    //!
    //! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only).
    //! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz.
    //! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control
    //!   module (TM4x129 class only).
    //! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only).
    //!
    //! \b ADC_CLOCK_RATE values control how often samples are provided back to the
    //! application.  The values are the following:
    //!
    //! - \b ADC_CLOCK_RATE_FULL - All samples.
    //! - \b ADC_CLOCK_RATE_HALF - Every other sample.
    //! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample.
    //! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample.
    //!
    //! The \e ui32ClockDiv parameter allows for dividing a higher frequency down
    //! into the valid range for the ADCs.  This parameter is typically only used
    //! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be
    //! with the in the correct range to use the divider.  The actual value ranges
    //! from 1 to 64.
    //!
    //! \b Example: ADC Clock Configurations
    //!
    //! \verbatim
    //!
    //! //
    //! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at
    //! // half the rate.
    //! //
    //! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1);
    //!
    //! ...
    //!
    //! //
    //! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC
    //! // clock of 20 MHz.
    //! //
    //! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24);
    //! \endverbatim
    //!
    //! \return None.
    //
    //*****************************************************************************
    void
    ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
                      uint32_t ui32ClockDiv)
    {
        //
        // Check the argument.
        //
        ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
        ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S));
    
        //
        // A rate must be supplied.
        //
        ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0);
    
        //
        // Write the sample conversion rate.
        //
        HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M;
    
        //
        // Write the clock select and divider.
        //
        HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) |
                                     (((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ;
    }