TM4C1290NCZAD: I2C Master Data Read

Greetings,

Q1: "Is that data setup time (I7) only one spec I should fulfill for read data latch in TM4C1290NCZAD ?" 

No - as the multi-value, multi-listing spec chart indicates - all specs must be observed & met.

Q2: "Does the falling edge of SCL of TM4C1290NCZAD needs for read data latch ?"

Yes - the falling edge of SCL triggers the latch of SDA.

Kindly note - if you employ the vendor's API - ALL of these I2C spec details are, 'Managed for You!'    (Hundreds here have succeeded - (Never) having glanced at the I2C spec table - by exploiting the API...)

Should we fulfill ' Data hold time (master) (I4) ' for read data latch in TM4C1290NCZAD ?

 I wonder why this spec specified by 'Nom' , not 'Min'.

※ We doesn't employ a vender's API.

Hi cb1,

  Thank you for answering all of the questions. 

cb1_mobile said:

user6246923

 I wonder why this spec specified by 'Nom' , not 'Min'.

The timing requirement is defined in terms of system clocks, not absolute time. Margin has been built into these specified parameters (in terms of system clocks) to take care of MIN condition. 

One purpose of these questions is an acquisition of objective criterion.
I am considering that those answers I received is not enough.
Additional question to you refers to attached file in detail.TI MCU I2C SCL-Spec rev02.pdf

user6246923 said:

I am considering that those answers I received is not enough.

You may also wish to consider that your (earlier) 'Formation of your questions was equally, 'Not enough!'

When such (unusual) 'high detail' (i.e. beyond the device's spec) is sought - it proves normal/customary to clearly, 'State that fact!'

Your opening post gave, 'No Clue' as to your real intent - which proved unfair to those who, 'rose to your aid.'     (And whose answers would 'well-satisfy' the vast majority of posters here.) 

The standard data hold time of SDA is from spec I4. To get a more specific answer you need to use a specific example. What frequency is the system clock and what is the targeted I2C speed?

Thanks Bob

I added to show our specific example and  "Question 4". 

→　attached file.

How should we derive the minimum hold time ?

Regards, higashiTI MCU I2C SCL-Spec rev03.pdf

When acting as a master, the I2C provides a 7 system clock hold time or 7 * 8.33nS = 58.3nS. As a slave it provides a 2 system clock hold time or 16.66nS. When acting as a master reading data from a slave, 0ns hold time is required as the data is sampled in the middle of the high period of SCL.

Hi Bob

I appreciate your help.

I have one more question. This is last question of my issue. 

　→　attached file

Regards, higashiTI MCU I2C SCL-Spec rev04.pdf

The reflection on SCL is not likely a problem for the TM4C129 as it is the master and it is driving the clock. If bad enough it could be a problem for the slave. Treat SCL as a transmission line. If you have not already done so, put the pullup resistor at the slave end of the SCL line to help terminate it. You might even add an AC coupled termination at the slave end. How long are your SDA and SCL lines? Are they PCB traces or wires? What value of pullup are you using and where is it placed?  

Happy Xmas Bob

The reflection on SCL itself doesn't matter for us becouse of being suppose those waveforms to be modified easily.

I do what I want to know truly whether the objective criterion of it exists.

Refer to attached file TI MCU I2C SCL-Spec rev05.pdf

Regards,

Not sure that I understand your question. The second method with 240 Ohm series resistor and the 4.7K pullup resistor at the end of the line farthest from the TM4C123 looks best to me.

Hi Bob

I'm sorry that my question gave some misunderstanding to you.

So I will send revised Question 6 to you

→　TI MCU I2C SCL-Spec rev06.pdf

Regards, higashi