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TM4C1290NCZAD: Freescale SPI Frame format and SP0 =1 / SPH =1 setting

Part Number: TM4C1290NCZAD

Hello team,

I received additional inquiry which is related to the following thread.

https://e2e.ti.com/support/microcontrollers/other/f/908/t/888076

 

Although Our customer configured SSICR0.FRFto 0x0 (Freescale SPI Frame Format), customer noticed the following description.

 

Datasheet 17.3.7.2 section

“If operating in Advanced/Bi-/Quad-SSI mode, the SP0 and SPH bits must be programmed to 0.”

 

This means, if customer set SSICR0.FRFto 0x0 (Freescale SPI Frame Format),

  1. the SP0 and SPH bits should be programmed to 0.”
  2. Or, Customer should set SSICR1.MODE = 0x0 (Legacy SSI mode)

Is that correct?

 

If customer set the following setting, could you consider unexpected issue will occur?

===============

SSICR0.FRFto 0x0 (Freescale SPI Frame Format) and SP0 =1 and SPH =1

 ==============

It is appreciated if your will share your advice /comments on this.

 Best regards, Miyazaki

  • Hi,

    Takayuki Miyazaki said:

    This means, if customer set SSICR0.FRFto 0x0 (Freescale SPI Frame Format),

    1. the SP0 and SPH bits should be programmed to 0.”
    2. Or, Customer should set SSICR1.MODE = 0x0 (Legacy SSI mode)

    Is that correct?

      If you want to use the QSSI mode then:

      The SP0/SPH should be 0/0.

      MODE should be 0x2 (Quad-SSI mode)

    Takayuki Miyazaki said:

    If customer set the following setting, could you consider unexpected issue will occur?

    ===============

    SSICR0.FRFto 0x0 (Freescale SPI Frame Format) and SP0 =1 and SPH =1

      Correct, if you want to use QSSI mode then don't set SP0/SPH to 1/1 or unexpected result.

      

  • Hi Charles,

    Thanks for your clarification and I’m sorry for confusing you. I seemed to write incorrectly. Customer configured SSICR0/ SSICR1 as follows.

    I mean, our customer set “ SPH = 1 and SPO = 1” under MODE = 0x3 (Advanced SSI Mode with 8-bit packet ).

    You mean, there is possibility that unexpected issue would occur under this setting. Is that correct?

     

    I noticed the following description.in datasheet( section 17.3.7.6).

    “Note: This Freescale SPI frame format configuration is only available when operating in Legacy SSI mode of operation.”

    This means, customer wants to use “Freescale SPI Frame Format with SPO=1 and SPH=1”, customer should set mode to “Legacy SSI mode”.

    Or, if customer wants to use “Freescale SPI Frame Format with SPO=0 and SPH=0”, customer is able to set MODE to “Advanced/Bi-/Quad-SSI mode.” .

    Is that correct?

     

    ======

    SSICR0 = 0x000002C7

    SCR – 0x02 (20MHz)

    SPH = 1

    SPO = 1

    FRF = 0x0 (Freescale SPI Frame )

    DSS = 0x7 (8bit-data)

     

    SSICR1 = 0x0000 01C2

    EOM = 0

    FSSHLDFRM = 0

    HSCLKEN = 0 ?(Use Input Clock)

    DIR = 1 (RX read direction)

    MODE = 0x3 (Advanced SSI Mode with 8-bit packet )

    MS =0 (The QSSI is configured as a master)

    SSE 1 (QSSI operation is enabled)

    LBM 0 (Normal serial port operation enabled.)

    ======

     

    Best regards, Miyazaki

  • Takayuki Miyazaki said:

    I mean, our customer set “ SPH = 1 and SPO = 1” under MODE = 0x3 (Advanced SSI Mode with 8-bit packet ).

    You mean, there is possibility that unexpected issue would occur under this setting. Is that correct?

     

    Hi Miyazaki-san,

      Yes, The QSSI only supports SPH=0 and SPO=0. Any other SPH/SPO combination will not work and produces unexpected results. 

    Takayuki Miyazaki said:

    This means, customer wants to use “Freescale SPI Frame Format with SPO=1 and SPH=1”, customer should set mode to “Legacy SSI mode”.

    Or, if customer wants to use “Freescale SPI Frame Format with SPO=0 and SPH=0”, customer is able to set MODE to “Advanced/Bi-/Quad-SSI mode.” .

    Is that correct?

    Your understanding is correct. If customer wants to use SPO=0, SPH=0 then use legacy SSI mode. 

  • Hi Charles,

    Just a quick note which (may) increase the flexibility of the MCU's SPI Module.    (We have used this successfully in the past - although we cannot find the exact project file - perhaps this poster may benefit.)

    The deployment of "a fast, simple series of logic gates" (may) enable the "exact" SPI Mode desired.    For example - the MCU may be ordered into "Freescale SPI Frame Format with SPO=0 and SPH=0" (which does not match the external SPI device's polarity and/or edge requirements) yet enable successful SPI transfers due to the external logic's (selective) signal modifications.   Note that (both) the signal level - and signal edge may be modified - so that, "Clashes between normally (incompatible) SPI Formats are Resolved!"

    This works best (easiest) w/a "single SPI Master" - so that SPI Clock can remain "uni-directional."   As SPI data moves along "2 different (and fortunately) independent pathways" - the data modification [edge or level "flip"] (usually) will succeed.    

    Propagation & other delays (are) expected - this "flexibility" may require that the SPI clock rate be dialed down...

    As a point of interest - might you know, "Why 'Advanced/Bi/Quad SPI Mode" is confined to "SPO = SPH = 0?"    Is this an MCU limitation or ... a "demand" of "Advanced/Bi/Quad" SPI devices?

  • Hi cb1,

      

    cb1_mobile said:
    As a point of interest - might you know, "Why 'Advanced/Bi/Quad SPI Mode" is confined to "SPO = SPH = 0?"    Is this an MCU limitation or ... a "demand" of "Advanced/Bi/Quad" SPI devices?

     I tend to think this is a MCU limitation. 

  • Charles Tsai said:

    Hi Miyazaki-san,

      Yes, The QSSI only supports SPH=0 and SPO=0. Any other SPH/SPO combination will not work and produces unexpected results. 

    Hi Charles,

    Could you elaborate what kind of unexpected results happen?

    Write error, Read error, damage hardware・・・・

    And let me know how the Advanced mode work. I can't find details in the data sheet.

    Best regards,

  • Midnight, empty office Greetings, Charles,

    With our group's possibly (inspired) SPI Flexibility design suggestion, "Kicked brutally curbside" - cb1 must choose:

    • use of cocked, loaded, raised to head level ... pistol
    • or await the "killer virus" ...  to finish the job

  • HI,

      Here is an QSSI project example. There is an entire section in the QSSI chapter talking about Advanced, Bi- and Quad- SSI Function. Normally a datasheet will describe the supported features and how to operate them. The datasheet will not describe what will happen using unsupported configurations. I don't think there will be damage hardware if you use SPO/SPH=1/1 but likely that the Data will not come out on the polarity/phase as expected. qssi.zip