Hello team,
I received additional inquiry which is related to the following thread.
https://e2e.ti.com/support/microcontrollers/other/f/908/t/888076
Although Our customer configured SSICR0.FRFto 0x0 (Freescale SPI Frame Format), customer noticed the following description.
Datasheet 17.3.7.2 section
“If operating in Advanced/Bi-/Quad-SSI mode, the SP0 and SPH bits must be programmed to 0.”
This means, if customer set SSICR0.FRFto 0x0 (Freescale SPI Frame Format),
- the SP0 and SPH bits should be programmed to 0.”
- Or, Customer should set SSICR1.MODE = 0x0 (Legacy SSI mode)
Is that correct?
If customer set the following setting, could you consider unexpected issue will occur?
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SSICR0.FRFto 0x0 (Freescale SPI Frame Format) and SP0 =1 and SPH =1
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It is appreciated if your will share your advice /comments on this.
Best regards, Miyazaki