This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM44L920: Confirmation of required input slew rate (rise time)

Part Number: RM44L920

Greetings.

Data sheet Section 7.1.1 Input Timings, state that the maximum t(in_slew) is 1nS. I would like clarification on this.

Does this mean that all logic input signals going into the controller must have a 1nS rise/fall time or faster? That would seem very fast. Standard LVC logic typically has a rise/fall time of 4nS.

Or, is this 1 nS criteria congruent with the minimum pulse width also shown in section 7.1.1? If so then:

What would be the required t(in_slew) for I/O pins, particularly interrupt driven pins?

Best Regards, Charlie

  • Hi Charlie,

    This parameter has mainly to do with the timing specifications for any interface with a "round trip" nature, e.g. SPI. The SPICLK max frequency specification also depends on how fast the other node can drive its outputs as well as their slew rate. This 1ns spec was included in the datasheet to indicate that the max SPICLK frequency specification assumes a 1ns slew rate for inputs. If this slew rate is higher, the appropriate adjustment needs to be made to the max SPICLK frequency possible. This is easily understood and obvious when looking at the SPI timings.

    This parameter has been removed from several Hercules parts' datasheets and will be removed from the RM44 datasheet as well as part of the next update.

    Regards, Sunil

  • Hi Sunil.

    Thank you for the fast response!

    For GPIO configured as input with interrupt, is there a maximum slew rate requirement? Specifically, GPIOB[0..3].

    We are using these pins in some cases as inputs with external with open drain drives, slew rate is ~ 1uS. Is this acceptable?

  • Hi Charlie,

    Yes, that should be okay. I presume you generate interrupt on a falling edge and the rise, even if over 1us, does not cause the MCU to detect oscillations around the L -> H switch-over point.

  • We will be detecting the rising edge of a OD signal which has a rise time of ~1us.

    Attached is a scope trace of our worst case. The green trace is our actual signal that we would want to interrupt on the rising edge.

  • All GIO pins have a configurable pull, which defaults to a pull-down. So the external pull-up has to override this internal pull-down as well. Can you configure the internal pull on this pin to be a pull-up and see that it speeds up the rise of the signal? It is not an issue either way, even if you get multiple toggles around the low-to-high transition point (CPU interrupt may not keep up).

  • Yes we can configure the internal GIO to pull up. You mentioned multiple toggles, will that be an issue with this slew rate?

  • I don't think it is an issue. There is no hardware debounce on the GIO pins. Typical interrupt latency is longer than this slew rate, so you will only really see a single interrupt even if there are multiple oscillations around the L->H transition point.