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CCS/RM48L530: issue about parity error

Part Number: RM48L530

Tool/software: Code Composer Studio

Dear team

I saw the following in RM48 datasheet and User's guide (“parity protection for peripheral RAMs”)

"If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error."

1  So If a parity error is detected in RAM, how does our CPU handle the error data read? Is it discarded and re-read? Or is it still used?

Do we have a recommended approach?

2  CPU's ECC failure ESM Group 3 channel 7: Is there a suggested solution for Flash Uncorrectable error?



  • Hello Susan,

    1. On any read access to peripheral RAM, the parity of the data will be checked. If a parity error is detected, the parity error bit in error and status register will be set. If error interrupts are enabled, also an interrupt would be generated. The CPU reads the data independent of parity error, and no data correction is made. Your application has to check the parity or parity error interrupt to ensure that the read data is valid.

    2. The 2-bit ECC error can be detected, but can not be corrected. FEDACSTATUS contains the type of error The error address is stored in FUNC_ERR_ADD register, and this register is not changed with the reset signal. If the error is caused by the ECC malfunction test, the application needs to clear the ESM status register since this error is expected for the ECC diagnostic test.  

  • Thank you very so much