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TM4C1290NCZAD: RAM testing with DMA enabled...

Part Number: TM4C1290NCZAD

Team,

Looking to develop a periodic RAM test for IEC60335-1 Class B. I have DMA running in the background, eg continuous ADC transfer to RAM buffer. I plan to run the RAM test inf a critical section (all interrupts disabled).

Do i have to take into account background DMA processing that might already be in operation, and if so, is there any information regarding this you would be able to point me at?

Thanks.

  • Hi,

      If your RAM test (e.g. March13 test) is reading/writing to the RAM buffer used for ADC transfer then you need to either stop the DMA before you run the RAM test or wait for the DMA transfer to complete before the test. Of course, you need to make sure the RAM buffer data has already been processed by the CPU. If your critical section is a different RAM area from the ADC RAM buffer then I don't see a problem having both running (RAM test and DMA) at the same time.