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TM4C1294KCPDT: ADC channel RS impedance

Guru 51405 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: TLV2461

Hello group,

Curios about interfacing discrete stacked ferrite chips or chokes that may improve TSHN encoding performance as a means for isolation of voltage divider higher RS impedance. Noteable the placement of very low dc impedance ferrites at the ADC channel input followed behind by much higher RS impedance divider circuit the idea. I past tested that isolation concept with what seemed good results at the time and later changed the position of ferrite stack to sit in front of voltage dividers.

Seemingly the idea for change was to attenuate any offending voltage transient or noise prior to the analog divider direct input to ADC channels. Perhaps the much lower impedance of a stacked ferrite chip (often 100 - 1k ohms) might be better served in direct placement with the channel inputs, if the RS impedance of the voltage divider is much greater than 10k ohms?

Is there any Wiki reports on how placement of stacked ferrite chips improve or otherwise lead to better performance of any TI ADC in production? Obviously stacked ferrite chips are used extensively around analog video devices for good reasons, though often at the point of signal interface to cables etc.. Yet until of late have we noticed any ferrite chips on TI production launch pads, least of all on ADC channel inputs.

What say the community?

   

  • Hello Gl,

    We haven't done any analysis of that for TM4C with our ADCs and don't have any reports on our end. A bit too system/application specific for us to really comment on what makes sense implementation wise there.

    That said, there is a TI document from the ADC group which talks about RLC filtering: https://www.ti.com/litv/pdf/sbaa108a

    Maybe that will be a useful read. Hopefully someone from the community can share their experiences.

  • Hi Ralph,

    Ralph Jacobi said:
    A bit too system/application specific for us to really comment on what makes sense implementation wise there.

    The converter has wild random acquisition points without configuring extensive oversampling and very high TSHN encoding values. Necessary to quiet digital rolling of displayed digits in 10's, 1's, rapidly 10ths position over 3 digit span. 

    Perhaps some of that is due to RS impedance matching rather than simply noise riding VREF, even if a decoupling filter may exist as part of the analog voltage divider circuit?  

    This AM re-ran Tina analysis for the analog divider circuits with very low ferrite resistance (400-600mohms). Either position did not show reduced RS impedance on the ADC channel input via AC/DC analysis. Instead the same RS impedance occurs relative to analog divider ground resistor R2 value, no matter where the inductor AKA ferrite chip was placed in the circuit.

    Oddly TI Tina only models inductors for evaluating DC resistance of a ferrite chip, so I believe that analysis is greatly flawed. However adding buffer amplifier series with analog divider such as TLV2461 reduce Tina analysis divider RS resistance (R2=4.87K) to 49.38 ohms, a vast improvement at a good production budget price. I use Tina Ohm meter for static AC/DC resistance analysis and must be removed for transient analysis or the real world results are skewed.

     

  • Ralph Jacobi said:
    Maybe that will be a useful read

    Not very much since the filter R2 resistor values are much lower than a typical HV divider network. The RS table 15-5 values seem way off from actual periodic signal behavior at specific TSHn encoding values. In this case 4k87 RS impedance should technically be configured next level or NSH(9K5), TSHN(32) yet produced results being >SNR intensive.

    It seems the tables 15-4/5 were derived from DC nonperiodic signals and RS(4k87) actually required NSH(R500), TSHN(8) to acquisition more quietly via periodic signals without excessive SNR injected into sample conversions FIFO data. These results seem contrary table 15-5 and RADC(2k5) is never considered when the actual SNR suggest it should be sum/dividen part of the RS circuit impedance each TSHN cycle. Perhaps it even divides RS impedance by some factor of RADC as it seems to reduce SNR to lower decibel levels and achieve faster sampling rates.

  • Hello Gl,

    I am not following entirely on your comments about Tables 15-4 and 15-5. Those tables are showing maximum Rs values to acquire accurate ADC data based on the sampling frequency, it doesn't mean recommended Rs values. Are you suggesting that you need an Rs higher than the datasheet specifies?

    Can you share a schematic of your setup so we can assess how your system setup may be impacting the results you are seeing?

  • Ralph Jacobi said:
    Those tables are showing maximum Rs values to acquire accurate ADC data based on the sampling frequency

    The point was more about TSHN encoding values relative to documented RS maximum for the sampling frequency. In other words the higher the RS circuit impedance the lower TSHN must be set to avoid Nyquist overrun and below any RS match shown in tables 15. Again R2 shown in your link above sets the RS value impedance according to Tina AC/DC probe analysis.

    Obviously we want RS value to set divider above LSB but not at MSB to allow for head room in +VREFP and have acquisitions that produce stable digital values. For argument sake RS (R2) value setting 680mV for 180VDC is well above ground SNR and allows fair amount of digital upward mobility yet well below MSB to account for transients. While higher R2 values according to table 15 mandates >TSHN encoding values, in exact opposition to the sample frequency. Again RADC somehow divides or chops the RS (R2) impedance shown in table 15 and TSHN must be lowered not matched. That is a good thing as the Nyquist SMPS rate increases according to table 15 the lower TSHN is configured. 

    Ralph Jacobi said:
    Can you share a schematic of your setup so we can assess how your system setup may be impacting the results you are seeing?

    Not system setup, rather the Nyquist sample rate impedance relative a periodic analog signal and RADC chopping RS impedance. There are no test conditions listed to confirm how table 15 was derived or why it ignores RADC 2K5 in the TSHN encoding. If table 15 RS maximum values were derived with RADC it has to have some affect on RS impedance. ADC electrical specifications Note (j) is placed on RADC too and seems to affect RS shown in tables 15 but is not discussed.