• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 473 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS570LS0332: Can't flash TMS570LS0332 chip with external XDS100v2 emulator

Kelvin Sweere
Prodigy 110 points
Part Number: TMS570LS0332

Tool/software: Code Composer Studio

Hi all,

 

Last week QJ Wang gave me the advice to buy a XDS100v2 to flash my TMS570LS0332 chip. The XDS100v2 has a 14-pins pinout and I use a 20-pins JTAG pinout for my embedded system. When testing with Code Composer it gives an error message: -180 (low power). When measuring the power the VCC is 3,3V and the core voltage of the MCU is 1,2V.

To check if my embedded device is the problem, I connected the TMS570LC Hercules dev-kit to validate/test the connection. When I’m not connecting the com-port, it gives the same error message (-180). When I connect the com-port, it gives a -183 (detected cable break). When I disconnect the external XDS100v2 and connect the onboard programmer of the Hercules dev-kit, it can flash.

I used this schematic:

Does anybody know what’s wrong?

Kind regards,

Kelvin S.

  • 0
    TI__Guru**** 186196 points

    Hello Kelvin,

    Do you use blue wires to connect the 20-pin JTAG connector and 14-pin JTAG connectors? Can you share the schematics (around MCU and JTAG header) of your PCB board?

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    I'm sorry for the late replay. 

    Kind regards,

    Kelvin S.

  • 0 in reply to Kelvin Sweere
    TI__Guru**** 186196 points

    Hello Kelvin,

    Are there external pull-up resistors for NRST and nPORRST? Those two signals should be pulled up on your board.

    JTAG nTRST should be pulled down via a resistor on your board.  

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    The NRST and the nPORRST both have a pull-up resistor of 4k7 and the nTRST has a 4k7 pulldown resistor. 

    I just discovered their was and mistake with the hardware interface and connected it probably. I tested the connection with the TMS570LC dev-kit and it worked. 

    When I connected it to my own embedded device I get this errormessage:

    [Start: Texas Instruments XDS100v2 USB Debug Probe]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\30045508\AppData\Local\TEXASI~1\
    CCS\ccs930\0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.
    This utility will load the adapter 'jioserdesusb.dll'.
    The library build date was 'Feb 13 2020'.
    The library build time was '18:30:11'.
    The library package version is '9.1.0.00001'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '4' (0x00000004).
    The controller has an insertion length of '0' (0x00000000).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the FTDI FT2232 with USB interface.
    The link from controller to target is direct (without cable).
    The software is configured for FTDI FT2232 features.
    The controller cannot monitor the value on the EMU[0] pin.
    The controller cannot monitor the value on the EMU[1] pin.
    The controller cannot control the timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    There is no hardware for programming the JTAG TCLK frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length failed.
    The JTAG IR instruction scan-path is stuck-at-zero.

    The test for the JTAG DR bypass path-length failed.
    The JTAG DR bypass scan-path is stuck-at-zero.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    The details of the first 8 errors have been provided.
    The utility will now report only the count of failed tests.
    Scan tests: 1, skipped: 0, failed: 1
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 1
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 2
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 3
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 4
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 5
    Some of the values were corrupted - 83.3 percent.

    The JTAG IR Integrity scan-test has failed.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.
    The details of the first 8 errors have been provided.
    The utility will now report only the count of failed tests.
    Scan tests: 1, skipped: 0, failed: 1
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 1
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 2
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 3
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 4
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 5
    Some of the values were corrupted - 83.3 percent.

    The JTAG DR Integrity scan-test has failed.

    [End: Texas Instruments XDS100v2 USB Debug Probe]

    Do you know what's wrong?

    Kind regards,

    Kelvin S.

  • 0 in reply to Kelvin Sweere
    TI__Guru**** 186196 points

    Hi Kelvin,

    I might be caused by the JTAG signal integrity on your own board. Please make sure the device is powered correctly (3.3V, 1.2V), and is clocked with proper crystal (5M~20MHz) or other clock source, etc.

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    When I measure the I/O voltage it is 3.3217V and the core voltage is 1.2078V.

    I use a xlh536010-000000 oscillator. This is the signal:

    I think the quality of the signal is because I measure the high frequency signal with a relative long probe cable. What do you think?

    Kind regards,

    Kelvin S.

  • 0 in reply to Kelvin Sweere
    TI__Guru**** 186196 points

    Hi,

    The 10MHz clock signal looks ok. 

    Can you check the JTAG clock at MCU TCK pin? Emulator provides this clock to MCU. The maximum TCK is 1MHz for xds100v2. If the setting uses higher frequency, please decrease it to 1MHz. 

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    I reduced the clock signal to 10 kHz, because of length difference of the jumper wires. 

    This is my TCK pin with 10 kHz: 

    Kind regards,

    Kelvin S.

  • 0 in reply to Kelvin Sweere
    TI__Guru**** 186196 points

    It is pretty clean. 

    Just checked your schematics, and found one error: The TEST pin should be connected to ground, but connect it to NTRST. When emulator pull this pin to HIGH, the MCU will enter test mode.

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    Well spotted!

    I cut the TEST trace and connected it to ground. But it still got the same error. 

    Kind regards,

    Kelvin S.

  • 0 in reply to Kelvin Sweere
    TI__Guru**** 186196 points

    Hi Kelvin,

    I am not sure if the MCU is powered on properly. The JTAG RTCK is the returned clock from MCU, and the TDO is also the output from MCU. You can check if any data comes out of the MCU on TDO and RTCK. I am sorry I am not familiar with the JTAG protocol.