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TMS570LS2124: Questions about SPNU499C document

Part Number: TMS570LS2124

Hi Expert,

There're some questions about the below content of SPNU499C document. Hope you could explain it more clearly. Thanks!

  • What's the meaning and how to use of four quadrants?
  • What's the quadrant protects, if set as Table 2-89 description?
  • What's the function and how to configure of the "PPROTSET0" each bit?

The above is about TUV certification, an urgent case. Thanks for support in advance!

 

Content of SPNU499C 

Best Regards

Rayna

  • Hello Rayna,

    Please take a look at the table 6-21 in Datasheet:

    Each peripheral select (PS) addresses a 1KB region. This region is then divided into four quadrants [3:0], with each quadrant being 256bytes. These quadrants are then assigned to individual peripheral module control/status registers, as specified in Table 6-21 of the datasheet.

    Some peripheral register frames fit within a quadrant, while some other peripherals take two quadrants:

    PS[x] frame size <= 256 bytes: 1 quadrant required                                                 for example: PS[16] for GIO

    PS[x] frame size >256bytes and <= 512 bytes: 2 quadrants required                       for example: PS[23] for FTU, or PS[22] for HTU1 and HTU2

    PS[x] frame size >512 bytes and <= 1kB: 4 quadrants required                                for example: PS[12] or PS[13] for flexray,

    The FlexRay controller takes two complete peripheral selects, so that it uses eight quadrants.

  • The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define the access permissions to the peripheral register frames. If the CPU attempts to write to a peripheral register for which it does not have the correct permissions, a protection violation is detected and an Abort
    occurs.

    Example: PPROTSET0 is one of the peripheral protection set register:

    Bit 0 is for PS0 Quadrant 0 protection set --> MibSPI5 takes 2 quadrants

    Bit 1 is for PS0 Quadrant 1 protection set

    Bit 2 is for PS0 Quadrant 2 protection set --> not used

    Bit 3 is for PS0 Quadrant 3 protection set

    Bit 4 is for PS1 Quadrant 0 protection set --> MibSPI3 takes 2 quadrants

    Bit 5 is for PS1 Quadrant 1 protection set

    Bit 6 is for PS1 Quadrant 2 protection set --> SPI4 takes 2 quadrants

    Bit 7 is for PS1 Quadrant 3 protection set

    Bit 8 is for PS2 Quadrant 0 protection set --> MibSPI1 takes 2 quadrants

    Bit 9 is for PS2 Quadrant 1 protection set 

    Bit 10 is for PS2 Quadrant 2 protection set --> SPI2  takes 2 quadrants

    Bit 11 is for PS2 Quadrant 3 protection set 

    ... ...