• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 29 subscribers
  • Views 420 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS570LS0332: ECC dabort Error

Jordan Cantillano
Intellectual 355 points
Part Number: TMS570LS0332

Tool/software: Code Composer Studio

We are using our functions to check flash CRC.

Also, we have enabled the ECC core for check ECC erros in flash.

The issue: We have a abort exception error: ATCM ECC Error if the Size input the CRC function have this value 0x0001F800U.

The function start checking at the address: 0x00000000.

This error is not triggered if we change the size value. Right now, it is 0x00012C00U.

Thanks

  • 0
    TI__Guru**** 186196 points

    Hello,

    When the flash is erased, the ECC for flash is also erased. If the program loaded to the flash is smaller than 0x1F800, the content at 0x1F800 is 0xFFFFFFFF, and it's ECC value at 0xF0403F00 is 0xFF which is not a valid ECC value. 

    This is why you get an ECC error when reading the data from 0x1F800.

  • 0 in reply to QJ Wang
    Intellectual 355 points

    Hello QJ Wang:

    Thanks for replying. I noticed the uncorrectable error address is 0x19B00. Before the_coreEnableFlashEcc_ calling the flash is full of 0xFF after the address 0x19B00.

    After the calling this address seems to be blocked.

    Does the_coreEnableFlashEcc_ function blocks the erased flash part?

    if it does, could the empty part be read without trigger the ECC Error?

    Thanks, and regards

  • 0 in reply to Jordan Cantillano
    TI__Guru**** 186196 points

    Hello Jordan,

    The function doesn't block reading the blank area of the flash. But if the ECC is enabled, reading the blank flash with invalid ECC will generate double bit ECC error and trigger the abort exception.

    One way is solve this problem is to use generate ECC for the whole flash using linker command file.

    Please check the "How to Guides" in our Hercules FAQ:

     

  • 0 in reply to QJ Wang
    Intellectual 355 points

    Hello QJ Wang:

    We already programmed configure the linker command file for generating ECC in the whole Flash following the guide.

    The problem still there.

    Is there other way to read the empty flash without trigger the ECC error?

    Thanks, and regards

  • 0 in reply to Jordan Cantillano
    TI__Guru**** 186196 points

    From your screenshot, the blank area doesn't have correct ECC. Otherwise, the memory window should show the correct content 0xFFFFFFFF rather than 0xFFFFFF8F.

    Another way is to calculate the CRC only for you application image instead of the whole flash.

  • 0 in reply to QJ Wang
    Intellectual 355 points

    QJ Wang:

    We need to calculated the CRC for a flash section, even if it used or not.

    Is there a way to verify is the ECC is generated by the CMD file?

    Also, why does _coreEnableFlashEcc_ function change the unused bits?

     

    The bits changed after run the line 450.

  • 0 in reply to Jordan Cantillano
    TI__Guru**** 186196 points

    After the ECC is enabled, all accesses to the program flash memory will be protected by SECDED logic embedded inside the CPU. When CPU reads data from flash, it calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged.

    If you erase the entire (256KByte) flash, then program a tiny “Hello World” into the part, most of the flash will still contain ECC errors. Opening CCS memory browser lets CPU read  flash content with wrong ECC code, this is why the displayed value is messy. 

    Line #450 is write 0x1 to bit 25 of Auxiliary Control Register (ACTLR) to enable the flash ECC.

    The following is example linker cmd for calculating flash ECC:

    MEMORY
    {
        VECTORS (X) : origin=0x00000000 length=0x00000020 vfill = 0xffffffff
        FLASH0 (RX) : origin=0x00000020 length=0x0005FFE0 vfill = 0xffffffff
        STACKS (RW) : origin=0x08000000 length=0x00001500
        SRAM (RWX) : origin=0x08001500 length=0x00006B00

    /* USER CODE BEGIN (2) */
    #if 1
        ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3)) length=(size(VECTORS) >> 3)
        ECC={algorithm=algoL2R4F021, input_range=VECTORS}

        ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3)) length=(size(FLASH0) >> 3)
        ECC={algorithm=algoL2R4F021, input_range=FLASH0 }
    #endif
    /* USER CODE END */
    }

    /* USER CODE BEGIN (3) */
    ECC
    {
        algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
        hamming_mask = R4 /* Use R4/R5 build in Mask */
        parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
        mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
    }
    /* USER CODE END */

    /*----------------------------------------------------------------------------*/
    /* Section Configuration */

    SECTIONS
    {
    /* USER CODE BEGIN (5) */
    /* USER CODE END */
        .intvecs : {} > VECTORS
        .text : {} palign=8 > FLASH0
        .const : {} palign=8 > FLASH0
        .cinit : {} palign=8 > FLASH0
        .pinit : {} palign=8 > FLASH0
        .data : {} > SRAM
        .bss : {} > SRAM
        .sysmem : {} > SRAM
    /* USER CODE BEGIN (6) */

    /* USER CODE END */
    }

  • 0 in reply to QJ Wang
    Intellectual 355 points

    QJ WANG:

    Thanks, we are going to check the CRC before enabling the ECC

  • 0 in reply to Jordan Cantillano
    Intellectual 355 points

    QJ Wang:

    Is there a way for disable the flash ECC after enable it?

    Thanks

  • 0 in reply to Jordan Cantillano
    TI__Guru**** 186196 points

    Hi Jordan,

    Yes, you can call " _coreDisableFlashEcc_();" to disable the flash ECC.