Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM
Hi.
Is there a recommendation from TI to use the EPI in the mode "Host-Bus 8/16 Mode Asynchronous Muxed Read/Write"´?
For this mode an address latch is needed, which stores the address in a latch by means of the signal ALE of the EPI.
At the moment in our board the implementation is like in your "TIDM-TM4CFLASHSRAM Reference Design".
Unfortunately, the data for this reference design was probably deleted from the TI website.
The data can still be found here: www.electronicsdatasheets.com/.../TIDM-TM4CFLASHSRAM
The address is passed through the latch 74*373A for ALE high or 74*573A for us and the address is held for ALE low.
Due to the time E18 of max. 4ns marked in the picture, it happens that there are still changes on the muxed address/data signals at ALE high.
At the output of the latch, depending on the constellation of address old, address new and data, there are short glitches on the address lines.
These glitches lead to malfunctions with the SRAM we use.
Is there a newer reference implementation from TI, which is recommended?