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TM4C1294KCPDT: recommendation from TI to use the EPI in the mode

Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM

Hi.

Is there a recommendation from TI to use the EPI in the mode "Host-Bus 8/16 Mode Asynchronous Muxed Read/Write"´?
For this mode an address latch is needed, which stores the address in a latch by means of the signal ALE of the EPI.

At the moment in our board the implementation is like in your "TIDM-TM4CFLASHSRAM Reference Design".
Unfortunately, the data for this reference design was probably deleted from the TI website.
The data can still be found here: www.electronicsdatasheets.com/.../TIDM-TM4CFLASHSRAM
The address is passed through the latch 74*373A for ALE high or 74*573A for us and the address is held for ALE low.

Due to the time E18 of max. 4ns marked in the picture, it happens that there are still changes on the muxed address/data signals at ALE high.
At the output of the latch, depending on the constellation of address old, address new and data, there are short glitches on the address lines.

These glitches lead to malfunctions with the SRAM we use.

Is there a newer reference implementation from TI, which is recommended?

  • Hi Frederik,

      I did some searches myself and can't find this reference design in ti.com either. Don't really know the reason though. I think the reference design is tailored for a specific SRAM module. If you are using a different SRAM with muxed mode then there some tweaking needed on the timing is not surprised. 

      The below timing diagram uses ALE for active high to latch the address. I guess you configure to use ALE low to latch the address. You are saying when the ALE is low, you are latching the address, correct?  I suppose if the address settles before the latch closes then you should be latching the right address. I don't really know what the glitches you are talking. If you have logic analyzer capture that shows what is supposed to be the right timing vs. the wrong timing then it will be more clear to me. In any case, wouldn't you add some delay to the ALE signal will help the situation?