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TMS570LS2124: Maximum Clock: HCLK

Part Number: TMS570LS2124

Dear everyone,

as part of the implementation of the safety mechnaism accorfing to the "TI safety manual" (SPNU511D") some questions occured concerning the DCC (dual clock compare) at the main clock HCLK maximum ratings.

Acoording to the datasheet (SPNS165B) the maximum system clock is specified with 180MHz not in chater 5.1 "Absolute Maximum Rating"  but in chapter 5.5 „Switching Characteristics for Clock Domains"

1. The first questions about the clock: Is it truely the absolut maximum clock? Background of the question is that it is desirable to run the CPU with the maxmimum possible clock (180MHz). Any inaccuracy of the clock three might exceed this maximum clock. So a small inaccuracy of e.g. 10ppm of the oscillator forces in worst case the HCLK to exceed the 180MHz.

With the use of a 16MHz oscillator with 10ppm:

HCLK = f(oscillator) * multiplicator(pll)

HCLK = 16MHz *( 1 + 10/1000000) * 11,25 = 180,0018MHz

So the specification will be exceeded only by the inaccuracy of the pll. Is this "little" violation of the specification problematic? If not, how big the deviation can be?

2. A further question is the DCC itselft. The DCC detects a deviation of the clock e.g. HCLK. This deviation range can be set by user. Is there a experience of how large this deviation should be? Or is it project specific? And how to figure out what is a good value?

Furthermore the DCC compares two clock with each other e.g. the main oscillator with the system clock. So the DCC dependent on the input osscilator accurancy. So the DCC can "only" detect a PLL failure or a faulty written PLL-configuration, am I right?

3. If the 180MHz is truely the maximum clock it has to be decreased for proper operation in case of deviations in the clock generation path, right. So the inaccurancy of the oscillator and the defined threshold of the DCC (e.g. 0,5%) had to be summed up and the clock has to be decreased by this value, right? Are there any other influences in the clock generation path to be concerned about, like a inaccurancy of the PLL-logic?

Thank you and kind regards

Konstantin

  • Hello,

    1. The maximum HCLK is 180MHz. The frequency tolerance/stability is a function of the end-application. Some applications may have more stringent requirements than others. 30ppm frequency variation should be fine for most of applications.

    2. Yes, the DCC can detect the PLL failure (for example PLL slip), and PLL settings was changed.

    3. Yes, if the crystall has a big PPM, and the PLL output is out of the valid range specified by your application, you need to change the PLL settings to lower the PLL frequency. The internal PLL noise is mainly caused by thermal which affects the VCO, the loop filter resistors