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TM4C123BH6PM: How to confirm all processes are complete of uDMA?

Kuerbis
Expert 4145 points
Part Number: TM4C123BH6PM

Hi Team,

 

The customer uses the CH11 and the primary side (SSI0TX) of uDMA. is operating in PeripheralScatterGather mode.

Is there a way to verify that all processes are complete?

They tried the following method, but it did not work.

- Check with uDMAChannelModeGet function

- Confirmed state register of HWREG (UDMA_STAT)

 

Thanks and Best regards,

Kuerbis

  • 0
    TI__Guru*** 128255 points

    Hello Kuerbis,

    If they have configured the code correctly then they should get an interrupt for that:

    Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. At the end of this transfer, the next transfer is started only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt is generated only after the last transfer.

    Also:

    When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the interrupt controller.

    When a μDMA channel generates a completion interrupt, the CHIS bit corresponding to the peripheral channel is set in the DMA Channel Interrupt Status (DMACHIS) register (see page 623). This register can be used by the peripheral interrupt handler code to determine if the interrupt was caused by the μDMA channel or an error event reported by the peripheral's interrupt registers. The completion interrupt request from the μDMA controller is automatically cleared when the interrupt handler is activated.

    Is that what they are looking for here or is there something different? Do they have interrupts configured for the DMA? 

  • 0 in reply to Ralph Jacobi
    TI__Expert 4145 points

    Hi Ralph

     

    Thank you for replying.

    The customer doesn’t want to use interrupt and wants to use poling.

    Is the CHIS bit in DMACHIS register poling still solution for poling?

    In this case, we need to mask an interrupt. Right?

    How to do it?

     

    Thanks and Best regards,

    Kuerbis

  • 0 in reply to Kuerbis
    TI__Guru*** 128255 points

    Hello Kuerbis,

    Polling for the DMACHIS doesn't make a lot of sense here because you would see the uDMA is finished but not necessarily that SSI is finished. The only scenario I can really think of using uDMA + SSI + Polling would be when they want to come back to check if SSI transfers are complete, and for that you would want to check the SSI Status register and look for the BSY bit to see if it is still transmitting.

    If they have something different in mind, please explain how the customer wants to use polling.