Arm-based microcontrollers forum - Recent Threads

AM2434: Trigger EnDat3 through external Interrupt via CAP

Florian Ertl — Mon, 03 Aug 2026 15:35:41 GMT

Part Number: AM2434

Hi,

is it possible to use EnDat3 in periodic-command code through triggering via an external interrupt the CAP-Input? I oriented myself on the routing example:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1452411/faq-lp-am243-routing-gpio-interrupts-to-pru-core

but i couldn't make it work.
Configuring Sciclient did work, but the PRU never registered an event.

Here the function i used:

int32_t routeGpio1ToIep0Cap0(uint16_t gpioPin)

{

struct tisci_msg_rm_irq_set_req req;

struct tisci_msg_rm_irq_set_resp resp;

int32_t status;

memset(&req, 0, sizeof(req));

memset(&resp, 0, sizeof(resp));

req.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

* GPIO0 source indexes 0...89 correspond to the individual

* GPIO0 pin interrupt outputs.

req.src_id = TISCI_DEV_GPIO1;

req.src_index = gpioPin; // 6

req.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID | TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

* PRU_ICSSG0 destination inputs:

* 4 = IEP0 CAP request 0

* 5 = IEP0 CAP request 1

* ...

* 9 = IEP0 CAP request 5

req.dst_id = TISCI_DEV_PRU_ICSSG0;

req.dst_host_irq = 4;

status = Sciclient_rmIrqSet(

&req,

&resp,

SystemP_WAIT_FOREVER);

return status;

}

LP-AM243x-Pin used: 48 (=PRG0_PRU0_GPO6/H2)

EnDat works with the IEP-Timer settings and CAP6.

Best regards,
Flo

PMP41042: PMP41042 - transformer cyntec VT-22247A power rating

zhang James — Mon, 03 Aug 2026 14:18:16 GMT

Part Number: PMP41042

Hi TI team

I have a little confusion about VT-22247A used in PMP41042. The transformers' core is PQ52/32/43.8. It seems like the power rating is<1kw, but it was actually used in 3.3kw system. Is there any reason to support the using? Looking forward for your answers, thank you!

LP-MSPM33C321A: LP-MSPM33C321 / XDS110 error:CS_DAP_0: Error: (Error -590 @ 0x0) / no DFU-mode

discher — Mon, 03 Aug 2026 13:47:29 GMT

Part Number: LP-MSPM33C321A
Other Parts Discussed in Thread: CCSTUDIO

Hello,

LP-MSPM33C321A / serial-number M3010001

For the first use in CCStudio (21.0.0.14_1.12.0 on win11) tries to update the firmware without success:

"The XDS110 failed to switch into the DFU programming mode."

I tried to update by xdsdfu- but same result. I can't change into DFU-mode.
After xdsdfu -m there is no change to DFU-mode, always runtime-mode

Following xdsdfu -e results in: Found 0 devices

Thanks

Dietmar

MSPM0C1104: Will I run into problems if I have the supply voltage change when using the MSPM0C1104

Parker Bondi — Mon, 03 Aug 2026 12:46:29 GMT

Part Number: MSPM0C1104

Hello TI Support,

I am working with the MSPM0C1104S8YCJR and have connected it via I2C to my battery management IC (BQ25120AYFPR). The BMIC provides power to the entire system from it's switching supply which on power up is defaulted to 1.8V. I would like to send a command on startup to this IC to change the voltage of this rail to 2.5V and then operate in a typical loop fashion from there.

When I setup my syscfg file I have had success with setting the VDD to 1.8V.

But I am constantly having issues where the device seems to be "bricked" and I have to go to the MSPM0_Factory_Reset_Tool again and again.

I wouldn't say that operating at 2.5V is causing the bricking. It is tough to pin down the exact sequence of events that cause this and I'm wondering if someone knows for certain that this is causing the issue or if it is something else I am doing. It is a problem for me because it is making my firmware development timeline extend beyond my deadline.

AM263PX-RESTRICTED-SECURITY: MPU_firewall

Sravya Kalluri — Mon, 03 Aug 2026 09:52:49 GMT

Part Number: AM263PX-RESTRICTED-SECURITY
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

From your response, it appears that you are concluding that SysConfig displays all available options for every SLV. However, this does not necessarily mean that there is a connection between them.

For example, even though R5SS0_0 is listed as an initiator for R5SS0_CORE0_AXIS_SLV and we enable it, it does not have any practical effect. Similarly, restricting it also does not make any difference.

If R5SS0_0 wants to access the R5SS0_0 TCMA, it will do so using its local address, not through the AXIS slave interface.

Could you clarify if our understanding is correct?

AM2612: AM261x issues configuring custom CiA402 PDOs using Beckhoff SSC Tool

Jim Tsai — Mon, 03 Aug 2026 08:30:54 GMT

Part Number: AM2612

Hi Experts,

I am working on a custom board featuring the AM2612 SoC and aiming to implement EtherCAT CiA 402 with custom PDO definitions. I am using the INDUSTRIAL-COMMUNICATIONS-SDK-AM261X (version 2026_00_00_06) and referring to the Official Documentation (EtherCAT SubDevice Beckhoff SSC Demo).

I have encountered two issues when using the Beckhoff SSC Tool (v1.5.3.0) to configure PDOs and generate the source code:

1. Missing TI_ESC_CiA402_8i3.xml in SDK release According to the SDK documentation and the README.txt under ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch/am261x/, there should be two XML files:

TI_ESC_8i3.xml
TI_ESC_CiA402_8i3.xml

However, checking the actual directory in SDK v2026.00.00.06 reveals that TI_ESC_CiA402_8i3.xml is missing (only TI_ESC_8i3.xml, tiescappl.xlsx, and README.txt exist).

Additionally, in the parent directory ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_subdevice/beckhoff_stack/patch/, there is a TI_ECAT.patch file. Is there a separate patch file required specifically for CiA 402 implementation?

2. Importing custom PDO Excel overrides CiA402_SAMPLE_APPLICATION back to 0 To work around the missing XML file, I modified TI_ESC_8i3.xml as follows:

Set CiA402_SAMPLE_APPLICATION from 0 to 1
Changed APPLICATION_FILE from tiescappl.h to cia402appl.h
Removed <ApplicationFile>tiescappl.xlsx</ApplicationFile>

When importing this modified XML into a new SSC project, CiA402_SAMPLE_APPLICATION is correctly set to 1 and APPLICATION_FILE is set to "cia402appl.h". However, after importing a custom Excel file containing custom PDO configurations (where Device Profile is set to 402 and objects conform to CiA 402 specifications), SSC Tool automatically:

Resets CiA402_SAMPLE_APPLICATION back from 1 to 0.
Changes APPLICATION_FILE to <project_name>.h.

Below is the step-by-step workflow of how I configured the project using the Beckhoff SSC Tool:

1. Step 1: Created a new project using my modified TI_ESC_8i3.xml configuration file.

2. Step 2 : Prior to importing the custom PDO Excel file, CiA402_SAMPLE_APPLICATION is set to 1, and APPLICATION_FILE is set to #include "cia402appl.h".

3. Step 3: Saved the project configuration under the name "test".

4. Step 4: Selected the custom PDO Excel configuration file (test.xlsx).

5. Step 5: Imported the custom PDO Excel configuration file.

6. Step 6: After the import completed, checking the Application node in SSC Tool shows that CiA402_SAMPLE_APPLICATION was automatically overridden to 0, and APPLICATION_FILE was updated to #include "test.h".

7. Details of my custom PDO configuration in the Excel file, where Device Profile is configured as 402 with CiA 402-compliant object dictionary entries.

Could you advise on the correct workflow to define custom PDOs via an Excel file without having SSC Tool force CiA402_SAMPLE_APPLICATION back to 0?

Environment Information:

SoC/Board: AM2612
SDK Version: ind_comms_sdk_am261x_2026_00_00_06
Tool Version: Beckhoff SSC Tool v1.5.3.0

Thank you for your assistance.

AM6442: Core to Core Communication

ganesh d — Mon, 03 Aug 2026 08:02:12 GMT

HI Ti team,

I am working on the AM64x platform with communication between A53 Core0 (Linux) and R5F Core0 (MCU+ SDK).

Currently, we are using the standard RPMessage/RPMsg framework for data transfer. However, our application requires higher throughput and lower latency for exchanging large amounts of data between the A53 and R5F.

Our target is to achieve:

Transfer size: 1 KB
Transfer latency: 50 µs (A53 -> R5F, R5F-> A53)

Could you please advise:

What is the recommended IPC framework for achieving the best performance between A53 Core0 and R5F Core0?
Is RPMessage/RPMsg still the recommended approach, or should we use a shared-memory (zero-copy) mechanism with mailbox notifications?
Does TI provide any reference implementation or example project for a zero-copy framework on AM64x?
Are there any recommended optimizations (e.g., shared memory configuration, VirtIO/RPMsg tuning, mailbox usage, DMA) to improve throughput beyond the standard RPMsg implementation?
Are there any benchmark results comparing standard RPMsg with a shared-memory/zero-copy implementation?

I am using SDK 09.02.01.10 RT-LINUX and for R5F MCU+SDK 10_01_00_32 Version and I want to optimize the IPC by adapting the new framework to be impacted in the same given SDK versions...Kindly advise on this..

Any recommendations or reference examples would be greatly appreciated.

Thank you.

Ganesh D

AM2612-Q1: Some questions about sbl_ospi_multicore_elf

Shuqing Zhou — Mon, 03 Aug 2026 02:57:11 GMT

Part Number: AM2612-Q1
Other Parts Discussed in Thread: SYSCONFIG, UNIFLASH

Hi team,

I'm asking this for my customer

We're developing the AM261 and refer to sbl_ospi_multicore_elf demo to develop the SBL.

1.As we all know, RBL should boot the SBL to OCRAM from external flash firstly, where define the SBL address in external flash? is it can be placed in any address of external flash?

2. is in makefile define the SBL run address in OCRAM? Is it can define in any address?

3. what's the protocol used when RBL boot SBL from external flash?

is it must reset the flash before SBL boot APP from external flash even the protocol used in SBL is same as the RBL used?

4, where to define the app address in flash?

5. where to define the APP run address in OCRAM?

6. In the TRM, it says RBL trys to boot the SBL from 0x00000, but why the FLASH address starts from 0x60000000

BRs

Shuqing

TMS570LC4357-EP: Intermittent issue with N2HET

Donald Lam — Fri, 31 Jul 2026 19:43:19 GMT

Part Number: TMS570LC4357-EP

Hello,

We are currently developing software on a TMS570LC4357-EP and are running into an intermittent problem with the N2HET module that we have difficulty root causing. We were hoping for some assistance in understanding what could affect this peripheral, to help figure out which part of our system (either software or hardware) could be causing this and whether or not you’ve seen similar issues in the past.

The context of the problem is this:
We use the N2HET peripherals as GPIO i.e. we disable the HTU and the HET controller. We also use a development probe (Lauterbach Trace32 probe) to debug our boards. When we issue resets from the probe to the HW board, the probe sends a command to the nRST pin to reset the MCU. The MCU remains powered on during this reset.

The N2HET works as expected most of the time but intermittently fails, about 1 in 10000 times, after we issue the reset command. During the startup sequence of our bootstrap, the N2HET would be unresponsive, after putting peripherals out of reset. It's as if the peripheral remains in a reset condition despite us using commands to get it out of reset. This issue remains until the next full electrical power cycle of the TMS570LC4357-EP.

When the issue happens, both N2HET1 and N2HET2 have all their all registers (control, direction, input, outputs, etc.) zeroed out and no longer editable. Reads to the HET input pins fail as they always return 0x00000000.

Resetting power domain pins (PDPWRDWNSET and PDPWRDWNCLR) makes no differences. Same with the VLCK CDDIS pins. We cannot seem to get the HET out of reset from that point onwards until we power cycle.

Our start up sequence up until the point of failure is as follows:

we erase core registers (R0 to R12)
we set FIQ, IRQ, Abort, Undefined and System modes,
1. FIQ = 10001
2. IRQ = 10010
3. Abort = 10111
4. Undef = 11011
5. System = 11111
We enable VFP Unit
We clear Floating point registers (D0-D15)
We set the stack pointers
We initialize the RAM memory
1. load and configure RAMCTRL,
2. enable global memory hardware initialization via MINITGCR
3. enable auto hardware initalization via MSIENA and wait for it to complete
4. disable global memory hardware initialization via MINITGCR
we bring peripherals out of reset, by doing this:
1. forcing the primary system register (0xFFFFFF00) CLKCNTL bit 5 to 0 (to forcefully disable peripherals),
2. setting all the PSPWRDWNCLRx to 0xFFFFFFFF, for PCR1, PCR2 and PCR3, then
3. forcing the primary system register CLKCNTL bit 5 back to 1 (to forcefully re-enable peripherals),

After this, the HET should have be brought out of reset and be operational but sometimes it isn’t.

We initially suspected a VCLK issue (errata GCM#58 when VCLK <= HCLK/4) but this would be strange: we assume by default the ratio is VCLK/HCLK = 1/2 at startup, up until peripherals are out of reset. Also, our custom PLL configurations happen later in the startup it sets HCLK = 150MHz and keep VCLK1 and VCLK2 at a div ratio of 1/2.

Any help or other theories on what could be affecting the system would be appreciated. Attached are the register snapshots at start of operation, prior to and after reset and shortly after N2HET issue is encountered.

e2e.ti.com/.../2112.Collected-register-values.zip

AM2631-Q1: AM263x Sysconfig: Need to disable Clock module.

Eugene K — Fri, 31 Jul 2026 18:30:03 GMT

Part Number: AM2631-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hello,

SDK states that Clock module is always enabled with any other module. Not quite sure why is there such a constraint. I want to use SDK drivers that do not need Clock and use Sysconfig to configure them. I also do not need another interrupt that I have no use for.

How do I disable auto creation of Clock module and reclaim one of RTI modules for my application and remove unneeded interupt?

Regards,
Eugene

TUSB9261DEMO: TUSB9261 binary

Dimitrios Pressas — Fri, 31 Jul 2026 15:59:46 GMT

Part Number: TUSB9261DEMO
Other Parts Discussed in Thread: TUSB9261

Hello,

I'm trying to figure out which binary fits best for the TUSB9261 demo devkit.

I've found the following:

TUSB926x_FW_v1.06.hex
TUSB926x_FW_v1.06_SATA_NO_POLARITY_SWAP.hex
TUSB926x_FW_v1.06_SATA_POLARITY_SWAP_BOTH.hex
TUSB926x_FW_v1.06_SATA_POLARITY_SWAP_RX.hex

Although the schematics indicate that it's the TX signals that are swapped (pins 56 and 57).

Could you please clarify which is the right binary to use with the dev kit?

Thank you in advance.

Kind Regards,
Dimitrios Pressas
Hardware Design Engineer
Advanced Micro Peripherals ltd.

SK-AM62A-LP-PINMUX-CONFIGURATION: DM/WKUP R5F doesn't reach main

Aakash Tegginamani — Fri, 31 Jul 2026 14:54:26 GMT

Part Number: SK-AM62A-LP-PINMUX-CONFIGURATION
Other Parts Discussed in Thread: SK-AM62A-LP, SYSCONFIG

Hi,

I was developing a application with MPU to be configured.

The DM/WKUP R5F core in SK-AM62A-LP does not reach main with MPU configurations but the MCU R5F does why so.

I wanted to setup MPU regions once it reaches main. but i dont have the flexibilty to do that. even with minimul MPU configurations generated by sysconfig, I cannot understand why it fails if i dont want to use MPU or disable MPU.

Even if i setup MPU regions in sysconfig they needs to be hard codded with start address.

can you tell me why or is it possible to reach main without MPU being setup for DM/WKUP R5F core.

Regards

Aakash

MSPM0C1105: PD0 timers are consuming significantly higher current in Standby modes than expected.

Asish Mondal — Fri, 31 Jul 2026 14:54:05 GMT

Part Number: MSPM0C1105

Hi Team,

I have some PD0 mode current issue regarding the operation of PD0 timers on the MSPM0C1105 in Standby modes.

TIMG14 operates in Standby 1 mode but consumes approximately 114 µA, which is significantly higher than our application requirement.
TIMG8 does not appear to operate in Standby 1 mode, although the datasheet indicates that it is supported.
TIMG2, when running in Standby 0 mode, also consumes approximately 100 µA.

Since TIMG2, TIMG8, and TIMG14 are all PD0 timers, could you please help us understand why these timers consume significantly higher current while operating in Standby modes? Is there any additional configuration or recommended approach to reduce the standby current while keeping the timer running?

We would appreciate your guidance, as our application requires the standby current to remain below 10 µA.

Thank you for your support.

LMR51420: LMR51420YFD:Excessive EMI and power supply noise on custom MyIR board design

hassan taha — Fri, 31 Jul 2026 13:29:12 GMT

Part Number: LMR51420

We are currently using the LMR51420YFD converter to power a MYIR based board system .

However ,during testing , we are experiencing significant electromagnetic emissions (EMI) that threatens to fail the compliance tests.

We need to implement hardware mitigation steps to suppress these emissions.

Are there specific ,proven EMI filter recommendations tailored for the LMR51420YFD to reduce these emissions?

Thank you for your assistance.

Best regards,

Hassan

AM263P4: Unable to debug sbl_ospi_multicore_elf project in CCS – Core0_0 runs continuously without hitting breakpoints

Gokul A Nair — Fri, 31 Jul 2026 10:49:44 GMT

Part Number: AM263P4

Hi Team,

I am having trouble debugging the Secondary Bootloader (SBL) project on my AM263Px Control Card.

SDK Version: mcu_plus_sdk_am263px_26_00_00_06
CCS Version: 20.5.0.28__1.11.0
Project: sbl_ospi_multicore_elf (imported from SDK)
Boot Mode: OSPI Boot Mode
Hardware Setup: AM263Px Control Card debug port connected to PC serial port for flashing and debugging.

Issue:
When I use the 'Debug Project' option in Code Composer Studio (CCS), Core0_0 starts running continuously. It does not hit any breakpoints, including the ones set in the main() function.

Notes:

I am successfully able to flash and debug standard application projects using this setup. The issue is strictly isolated to this SBL project.
I am unsure if using "Debug Project" in OSPI boot mode is the correct procedure for debugging the SBL itself.

Could you please guide me on the correct sequence to debug the SBL project? Any help to resolve the breakpoint issue would be highly appreciated.

Thank you!

[FAQ] AM2611-Q1: How to erase flash from CCS Flash Plugin

Aswin Sankar — Fri, 31 Jul 2026 05:45:28 GMT

Part Number: AM2611-Q1
Other Parts Discussed in Thread: UNIFLASH

Hi,

How can I erase external flash via CCS Flash plugin

[FAQ] AM2611-Q1: How to enable VLAN in LwIP

Aswin Sankar — Fri, 31 Jul 2026 05:31:30 GMT

Part Number: AM2611-Q1

Hi,

I want to enable VLAN in LwIP. The LwIP stack should untag VLAN tagged packets and provide it to the application.

While egress, the LwIP should tag the packet and provide it to hardware. How can this be done?

MSPM0G3519: CRC16 not working for mspm0

Abayomi Babatola — Fri, 31 Jul 2026 05:23:40 GMT

Part Number: MSPM0G3519
Other Parts Discussed in Thread: SYSCONFIG,

Hello,

For a project that needs CRC16 calculation, I have tried to get the microcontroller CRC peripheral to do the calculation but it does not work.

I have already tried the CRC32 on the microcontroller and it works just fine.

What could be the problem or is there a sample CRC16 project that I could use as a guide.

Thanks.

AM2612: Pin delay for AM2612 ZNC

Sophie Chen(DLP) — Fri, 31 Jul 2026 03:12:15 GMT

Part Number: AM2612

Hi Team,

Seyond is asking for the pin delay table for the AM2312 ANC package. Could we provide such table for them for layout?

Also I notice that we state the trace mismatch on the datasheet. Do this parameter contains the pin delay? And they only need to pay attention to the PCB trace?

MSPM0L1306: MSPM0L1306: Simultaneous LIN break-threshold AND UART framing-error detection

Zaigham Khawaja — Thu, 30 Jul 2026 23:34:34 GMT

Part Number: MSPM0L1306
Other Parts Discussed in Thread: MSPM0G3507

For the MSPM0L1306,
Framing-error detection is required for LIN conformance, including framing errors in the sync, PID, data, and checksum fields.
But the TRM states: "Framing errors and break conditions are not set when LIN mode is enabled."

For LIN break-threshold detection, it must be operated in LIN Mode, utilizing LINCNT, LINC0, and the following LINCTL settings, which stops the framing-error detection as the side-effect.

Newer MSPM0L devices (MSPM0L211x/122x) come with UNICOMM-UART which has an additional setting LINCTL.EN_FRM_ERR, allowing framing-error reporting during LIN operation:

But the MSPM0L1306 UART does not provide this field:

So,
How can framing-errors be detected on the MSPM0L1306 while using the LIN counter for break-threshold detection?

If simultaneous operation is not supported, what is TI’s recommended implementation for meeting both requirements?

1. Break detection with an 11-Tbit threshold
2. Framing-error detection for LIN Conformance Tests

Thanks in advance,
Zaigham

AM6422: sciclient

MICHAEL AIELLO — Thu, 30 Jul 2026 18:21:35 GMT

Part Number: AM6422

DEVICE: AM64

OS: Freertos

COMPONENT: CMPEVT_INTRTR0 (interrupt router)

Need information on how to create an interrupt mapping for connection of CPSW0_CPTS_COMP_0 to interrupt controller (VIM) for R5FSS0_CORE0,

According to the documentation source inputs for CMPEVENT_INTROUTER_OUTP_16 trough 23 are available.

Insufficient information on how to set this up using SciClient interface.

AM2612: AM2612 / AM2634: High temperature observation (>50°C) during idle/low-load states and request for thermal mitigation strategies

Jack — Thu, 30 Jul 2026 17:44:45 GMT

Part Number: AM2612
Other Parts Discussed in Thread: AM2634, SYSCONFIG

Hi TI Team,

Our robotics customers are currently evaluating the AM2612 (Dual-core R5F) and AM2634 processors for their upcoming projects. Recently, an issue has been raised regarding the operating temperature.

During their tests, they observed that the MCU surface temperature exceeds 50°C even in idle or low-load states. In comparison, they have tested a competitor's MCU (NXP i.MX RT1180) under similar conditions, which operates in the 30°C range. This has raised concerns regarding thermal management for the AM26x devices.

To address the customers' concerns, we would like to request support on the following points:

Expected Thermal Profile: What is the normal or expected operating temperature range for the AM2612 and AM2634 during idle or light-load conditions?
Software / Clock Management: Is it possible to reduce system power consumption (and consequently heat dissipation) by disabling the clocks or power domains of unused subsystems while maintaining full clock speed on the active R5F cores? If so, could you provide guidance or examples on how to properly configure this?
Thermal Design Guidance: Could you share comprehensive Thermal Design Guidelines for these devices? We are specifically looking for both hardware (PCB layout, thermal vias, mechanical heat dissipation) and software strategies to effectively lower the operating temperature.

Thank you in advance for your support.

Best regards,
Jack

AM2754-Q1: AM275x USB Stack

Lippold Haken — Thu, 30 Jul 2026 17:06:30 GMT

Part Number: AM2754-Q1

Hi! We are writing ARM and C7x code and running it on the AM275x development board. We are also in the process of producing our own board design using the AM27542AF, for use in our future products.

I am looking for the AM275x USB software package; I have seen reference to it in many places, but cannot locate the package itself. What company supplies this package? I am looking for software including the USB controller driver, third-party USB stack (if available), AM275x porting layer, documentation, and example projects for FreeRTOS SDK 12.00.00.22.

Thanks!
Lippold Haken / Haken Audio / www.HakenAudio.com

AM2434: Unable to flash bootlader at AM324X-LP

Sergej Sergeyuk — Thu, 30 Jul 2026 15:15:06 GMT

Part Number: AM2434
Other Parts Discussed in Thread: UNIFLASH

We're looking for upgrade our legacy C6424 based HW for a new AM243x platform.

My setup is: AM324X-LP connected to Win10 + ccs2100 + mcu_plus_sdk_am243x_12_00_00_27 + ind_comms_sdk_am243x_2026_00_00_06 + motor_control_sdk_am243x_09_02_00_12

AM324X-LP boot mode: UART. PC can receive sequence of "c" at COM4 at 115200

I'm trying to flash the pre-built version of the "sbl_null.release.hs_fs.tiimage" via "sbl_uart_uniflash.release.hs_fs.tiimage" as example.

CMD: python uart_uniflash.py -p COM4 --cfg=sbl_prebuilt/am243x-lp/default_sbl_null.cfg

CFG:

--flash-writer=sbl_prebuilt/am243x-lp/sbl_uart_uniflash.release.hs_fs.tiimage
--file=sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0

Problem:

uart_uniflash.py successfully sending the sbl_uart_uniflash to device but then communication stopped. My assumption is the control has to be given to sbl_uart_uniflash code and it should continue with the reading from COM and flash received data. But there's no such communication. Error message:

C:\ti\mcu_plus_sdk_am243x_12_00_00_27\tools\boot>python uart_uniflash.py -p COM4 --cfg=sbl_prebuilt/am243x-lp/default_sbl_null.cfg
Parsing config file ...
Parsing config file ... SUCCESS. Found 2 command(s) !!!
Executing command 1 of 2 ...
Found flash writer ... sending sbl_prebuilt/am243x-lp/sbl_uart_uniflash.release.hs_fs.tiimage
Sent flashwriter sbl_prebuilt/am243x-lp/sbl_uart_uniflash.release.hs_fs.tiimage of size 308909 bytes in 27.84s.
Executing command 2 of 2 ...
Command arguments : --file=sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x0
Sending sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage: 0%| | 0/282197 [00:00<?, ?bytes/s]
send error: expected NAK, CRC, EOT or CAN; got b'0
send error: expected NAK, CRC, EOT or CAN; got b'1'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: expected NAK, CRC, EOT or CAN; got b'0'
send error: error_count reached 10, aborting. Sending sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage: 0%| | 2/282197 [02:17<10808:27:50, 137.89s/bytes]
[ERROR] XMODEM send failed, no response OR incorrect response from EVM OR cancelled by user,
Power cycle EVM and run this script again !!!

COM port stays connected at WIN10 and I still can see the "c" stream immediately after of error described above.

Any suggestions?

AM2434: AM2434: EtherCAT FWHAL interrupts never fire when registered at init, work when re-registered later

Tal Shvartzberg — Thu, 30 Jul 2026 11:16:31 GMT

Part Number: AM2434
Other Parts Discussed in Thread: LP-AM243

Hardware and software: LP-AM243 (AM2434 ALX), ICSSG1, Industrial Communications SDK 2026.00.00.06 (prebuilt ethercat_subdevice_icss_fwhal library), MCU+ SDK 12.00.00.26, R5F0-0 FreeRTOS.
We run a third-party EtherCAT slave stack (SOES) on top of the EtherCAT FWHAL (tiescbsp), not the Beckhoff SSC.

The port works end to end: the ESC firmware boots, masters scan the slave, it reaches OP in DC-Synchron at 1 kHz, mailbox CoE and FoE work, and it has run multi-day soak tests.
The question is only about interrupt delivery.

Symptom:
We call bsp_init followed by bsp_start_esc_isr, the same placement your SSC integration uses in tieschw.c HW_EscInit. With that, EcatIsr, Sync0Isr and Sync1Isr are never invoked. Not once, no HOST_AL_EVENT, no SYNC events, while the ESC is fully functional through polling.

What we verified:
PRUICSS_intcInit ran with the tiesc_pruss_intc_mapping.h data. PRUICSS_registerIrqHandler succeeded and HwiP_construct enables the VIM lines, we confirmed the enables. Manually injecting the system events into the INTC invokes the registered handlers, so the INTC to VIM to handler chain is healthy. We also handle the stale-latch behavior: we hold the AL event mask at zero through the whole init so no event can latch before handlers exist, since we observed the PRU firmware will not re-raise an event that is still latched uncleared in the INTC.

The part we cannot explain:
If we call PRUICSS_registerIrqHandler again for the same event outputs (evtOut 3, 1, 2) and the same interrupt numbers (interrupt_offset plus 3, 1, 2) with our own thin handlers AFTER our stack initialization completes, and only then open the AL event mask, delivery is perfect: PDI and SYNC0 at exactly 1 kHz, stable for days. The same registrations made during init, whether by bsp_start_esc_isr or by our own code at the same spot, stay dead.
So the difference is when the registration happens relative to something in the init sequence, not whose handler symbols are registered. Your SSC demo registers at init time and works, so the SSC init apparently does something between registration and cyclic operation that a third-party stack must replicate, and we would like to know what it is.

Questions:

Does the EtherCAT PRU firmware or the FWHAL invalidate or depend on host ISR registrations made before some specific point in the bring-up (a firmware command, a register write, an INTC state)?
Is there a prescribed ordering between bsp_init, firmware start, ISR registration and the first AL event mask write for non-SSC stacks?
Is re-registering the evtOut handlers after stack init a supported pattern, or does it work by accident?
What does the SSC initialization do after bsp_start_esc_isr that arms delivery, so we can do the equivalent?

We link the prebuilt FWHAL library, which is built without ENABLE_PDI_TASK and ENABLE_SYNC_TASK, and our handler bodies run in FreeRTOS tasks woken from the callbacks.

Happy to provide our init sequence or captures.