Arm-based microcontrollers forum - Recent Threads

AM2432: HSR and PRP storm prevention

Andrea Politano — Thu, 24 Sep 2026 13:49:53 GMT

Part Number: AM2432

I am using AM2432 with the Industrial SDK 11.00.00.08.

Our product uses the HSR and PRP stack. We are conducting Storm Tests to verify the robustness of our device (such as ARP Storm Requests).

At first, during storm requests this error appeared:

[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
                                                                  pbuf_free: p->ref > 0ASSERT: 85.697915s: C:/am243x-mcu-plus-sdk/mcu_plus_sdk/source/networking/lwip/lwip-stack/src/core/pbuf.c:pbuf_free:755: 0 failed !!!

I suppose it was because there wasn't any more memory left to allocate to the packets.

I noticed, however, that the Profinet demo enabled storm prevention, so I added the function:

{
...
    if(status == SystemP_SUCCESS)
    {
        RedProtocolStart(&hsrPrphandle, prusshandle);
        /*Load the default PCP to Queue mapping*/
        hsrprp_loadPCPtoQueueMap(emachandle, default_pcp_2_queue_map);
        hsrprp_enableBroadcastStormPrevention(emachandle);
    }
...
}

static int32_t hsrprp_enableBroadcastStormPrevention(ICSS_EMAC_Handle emacHandle)
{
    ICSS_EMAC_IoctlCmd ioctlParams;
    ICSS_EMAC_StormPrevention *stormPrevention;
    int32_t status;

    ioctlParams.command = ICSS_EMAC_STORM_PREV_CTRL_INIT_BC;
    ioctlParams.ioctlVal = NULL;

    status = ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_1, &ioctlParams);

    status &= ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_2, &ioctlParams);

    if (status == SystemP_SUCCESS)
    {
        stormPrevention = (ICSS_EMAC_StormPrevention *)((ICSS_EMAC_Object *)emacHandle->object)->stormPrev;
        stormPrevention[0].creditsBC = 100U;
        stormPrevention[1].creditsBC = 100U;

        ioctlParams.command = ICSS_EMAC_STORM_PREV_CTRL_RESET_BC;
        status = ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_0, &ioctlParams);
    }

    if (status == SystemP_SUCCESS)
    {
        ioctlParams.command = ICSS_EMAC_STORM_PREV_CTRL_INIT_UC;
        status = ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_1, &ioctlParams);
        status &= ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_2, &ioctlParams);
    }

    if (status == SystemP_SUCCESS)
    {
        stormPrevention[0].creditsUC = 100U;
        stormPrevention[1].creditsUC = 100U;

        ioctlParams.command = ICSS_EMAC_STORM_PREV_CTRL_RESET_UC;
        status = ICSS_EMAC_ioctl(emacHandle, ICSS_EMAC_IOCTL_STORM_PREV_CTRL, ICSS_EMAC_PORT_0, &ioctlParams);
    }

    if (status != SystemP_SUCCESS)
    {
        DebugP_log("Failed to enable ICSS EMAC broadcast storm prevention\r\n");
    }

    return status;
}

I didn't add the credit refresh part that's in the specific Profinet task PN_background_task, because I saw that it's already handled in Lwip2Emac_periodicFxn().

In this way the failed assert no longer occurs. However, I noticed that it still doesn't reply to ping during the storms, whereas with Profinet it was able to respond even during a storm.

How can I investigate this further? What am I missing?

Thank you,

Best Regards,

Andrea

AM263P4: ARM Cortex R5F FIQ interrupt and FPU context saving

Khalil Maton — Thu, 24 Sep 2026 11:29:28 GMT

Part Number: AM263P4

Hello,

In my case, I am not manually saving the FPU context but I have rebuilt the SDK with the HWIP_FPU_CONTEXT_SAVE_RESTORE_ENABLE flag in order to save/restore the FPU context in the HwiP_fiq_handler but it still doesn't work and the FPU registers are randomly corrupted by the FIQ. When I configure the interrupt as an IRQ then it works fine.

Consider this code, executed in a FreeRTOS task (I also have called the vPortTaskUsesFPU in the task even thoug this shouldn't be relevant for an FIQ):

vac_val has a value of -10.88 but the check passes randomly, when I looked into the assemply and the registers, it seems that the value in the FPU was corrupted

This is how it looks like when the registers are not corrupted:

Could you please provide any advice on how to fix this issue, many thanks in advance

Note: I am using mcu_plus_sdk_am263px_26_00_00_06 SDK and ti_cgt_arm_llvm_4.0.4.LTS compiler

AM263P4: Questions regarding the encryption keys: MEK (Master Encryption Key) and MPK (Manufacturer Public Key).

makoto yamashita — Thu, 24 Sep 2026 09:45:07 GMT

Part Number: AM263P4

Where are the MEK (Master Encryption Key) and MPK (Manufacturer Public Key) stored in which functional blocks of the SoC?

Requested response date: September 28, 2026

MSPM0L2228: LP-MSPM0L2228: Board bricked after erasing NONMAIN memory via UniFlash

Sarah Al zawaideh — Thu, 24 Sep 2026 08:58:28 GMT

Part Number: MSPM0L2228
Other Parts Discussed in Thread: UNIFLASH,

I was following the bootloader example MSPM0 Customer Secure Code and Bootloader (CSC) User’s Guide — Secure Booting User's Guide 1.1.0.x documentation for the MSPM0L2228 LaunchPad.

During the process, I performed a Mass Erase / Factory Reset in UniFlash, but I mistakenly set the Erase Method to: "Erase MAIN, DATA, and NONMAIN memory".

After doing this, the LaunchPad is no longer responding, and I am unable to reset it.

Is there a hardware/SW recovery procedure to restore the NONMAIN flash area on this specific LP-MSPM0L2228?

How can I recover/re-program the factory configuration into NONMAIN using UniFlash or Code Composer Studio?

Thanks for your help

AM6422: AM6422: UART1 RX Held Low During Boot Occasionally Interrupts Autoboot and Enters U-Boot Console

Yan Wang — Thu, 24 Sep 2026 08:16:11 GMT

Part Number: AM6422

Hi TI Team,

We are using an AM6422 device, and UART1 is connected as shown in the attached schematic.

UART1_RXD: Ball E15
UART1_TXD: Ball E14
UART1 is configured as the debug console and outputs boot logs during startup.
The UART path includes an ADuM342E digital isolator and an external USB-to-UART bridge.

System Configuration

The USB-UART bridge is powered from USB 5V.
The ADuM342E VDD1 side is powered from USB 5V.
The ADuM342E VDD2 side is powered from the AM6422 board 3.3V rail.
When the USB cable is unplugged:
- The USB-UART bridge is unpowered.
- ADuM342E VDD1 = 0 V.
- ADuM342E VDD2 remains powered at 3.3 V.
UART1 is used only for debug logging during boot.

Observed Behavior

During power-up, when SoC_DEBUG_RX (UART1_RXD) remains at a constant low level, the AM6422 occasionally enters the U-Boot console instead of continuing the normal boot process.

Observed frequency:

RX held LOW: approximately 1 out of 5 boots enters the U-Boot prompt.
RX held HIGH: 0 failures observed, system always boots normally.

The behavior is intermittent and does not occur on every power cycle.

Additional Observations

When SoC_DEBUG_RX is continuously high, the system boots normally every time.
When SoC_DEBUG_RX is continuously low, the system may stop at the U-Boot prompt.
We do not observe intentional UART traffic on the RX line during this time.
The issue appears to be related to the state of UART1_RX during the boot sequence.
The problem is reproducible when the USB-UART side is not powered.

Questions

Is there any known mechanism in the AM6422 boot flow or U-Boot implementation where a continuously asserted UART RX signal can be interpreted as incoming data and cause entry into the U-Boot console?
Can a UART RX line that remains low be interpreted as a BREAK condition, framing error, or other special UART event during boot?
During startup, which software stage monitors UART1 RX and could potentially interrupt the boot process?
- ROM Bootloader
- SPL
- U-Boot proper
Is there a recommended idle state for UART1_RX during boot? Should the RX pin always be pulled high when no valid UART source is present?

5.Are there any AM6422-specific registers, boot settings, or U-Boot configurations that we should check to better understand this behavior?

Any guidance or debugging suggestions would be greatly appreciated.

Thank you.

TMS320F28377D: Customer need suggestions on the reported issue_Request for Failure Analysis Report

Venu CK — Wed, 23 Sep 2026 15:45:48 GMT

Part Number: TMS320F28377D

Hello Team,

Good day!
We have received 9 RMA boards from our customer that were reported as failing in the field.

During our debug analysis, we identified component issue with the following three-part numbers. These parts were supplied under a single invoice.

We kindly request that you review our analysis report and provide your failure analysis report. If required, we are ready to send the defective samples for further investigation.

Out of the nine RMA boards, rework has been completed on four units. The remaining five units are currently under rework, and the analysis is ongoing.

We look forward to your support and feedback at the earliest convenience.

UCC27524DR

LMR23630APDRRR

TMS320F28377DPTPT

Please help to advise on the issue.Ffailure board analysis report.xlsx

AM13E23019: AM13E230x: Timer clocked from LFCLK generates interrupts at 2x frequency depending on MCLKDIV2/MCLKDIV4 configuration

Danylo Plotskykh — Wed, 23 Sep 2026 15:09:36 GMT

Part Number: AM13E23019

Unexpected TIMGx behavior was observed on an AM13E23019 when MCLK is sourced from SYSPLL.

TimerGx is explicitly configured to use LFCLK (32.768 kHz) as its clock source. Therefore, its operating frequency is expected to remain independent of the MCLK clock source and MCLK divider configuration. However, when MCLK is sourced from SYSPLL, TimerG4 generates periodic interrupts at approximately twice the expected frequency under specific MCLKDIV2/MCLKDIV4 configurations.

With MCLK sourced directly from SYSOSC, the same timer configuration produces the expected period of approximately 1007 µs. When MCLK is switched to the SYSPLL clock path, the period changes to approximately 500 µs, even though the timer continues to use LFCLK.

The system uses the following clock sources:

SYSOSC = 32 MHz
LFOSC = 32.768 kHz
MCLK can be sourced either directly from SYSOSC or from SYSPLL

Timer configuration

TimerG4 is explicitly configured to use LFCLK:

// tim_freq: lfosc_freq / (div_ratio * (prescaler + 1))

// tim_freq: 32768 / (1 * (2 + 1)) = 10922 Hz

DL_TimerG_ClockConfig tim_clock_cfg = {

.clockSel = DL_TIMER_CLOCK_LFCLK,

.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,

.prescale = 2u,

};

DL_TimerG_setClockConfig(TIMG4, &tim_clock_cfg);

DL_TimerG_TimerConfig tim_cfg = {

.period = 10u,

.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,

.startTimer = DL_TIMER_STOP,

.genIntermInt = DL_TIMER_INTERM_INT_DISABLED,

.counterVal = 0u

};

DL_TimerG_initTimerMode(TIMG4, &tim_cfg);

DL_TimerG_enableInterrupt(TIMG4, DL_TIMER_INTERRUPT_ZERO_EVENT);

DL_TimerG_enableClock(TIMG4);

DL_TimerG_startCounter(TIMG4);

The timer frequency is approximately 32768 / (1 × (2 + 1)) = 10922 Hz. With a period value of 10, the expected interrupt period is approximately 1 ms ≈ 1007 µs

Observed behavior

When MCLK is sourced directly from SYSOSC, TimerGx operates as expected and generates interrupts with a period of approximately 1000 µs. When MCLK is sourced from SYSPLL, the same TimerGx configuration produces a period of approximately 500 µs.

This occurs even though the timer clock source remains .clockSel = DL_TIMER_CLOCK_LFCLK and the LFCLK source itself is unchanged.

The behavior appears to depend on the configuration of MCLKDIV2 and MCLKDIV4. In particular, the issue occurs when the two dividers use different division ratios. When both dividers are configured with the same ratio, the timer operates as expected.

For example, the following configurations operate correctly MCLKDIV2 = DIV2 and MCLKDIV4 = DIV2 or MCLKDIV2 = DIV1 and MCLKDIV4 = DIV1. This suggests that the MCLK divider configuration may have an unexpected effect on the LFCLK clock domain or on the clock path used by TimerGx.

Expected behavior

Since TimerG is explicitly clocked from LFCLK, its frequency should depend only on the LFCLK source, timer clock divider, prescaler, and period.

For the following configuration:

LFCLK = 32768 Hz

Prescale = 2

Period = 10

Clock divider = 1

the timer period is expected to remain approximately 1000 µs, regardless of whether MCLK is sourced from SYSOSC or SYSPLL and regardless of the MCLKDIV2/MCLKDIV4 configuration. In particular, changing the MCLK source or its dividers should not change the frequency seen by a timer that is explicitly clocked from LFCLK.

Reproduction in independent projects

To exclude application-specific code or interactions with other peripheral initialization, two independent projects were created with otherwise equivalent TimerG configurations.

In the first project, MCLK was sourced from SYSOSC:

and TIMG4 was configured to 1ms period:

In the second project, MCLK was sourced from SYSPLL :

and TIMG4 has the same configuration:

The behavior was reproduced consistently:

With MCLK sourced from SYSOSC, the timer period was 1000 µs:

With MCLK sourced from SYSPLL and the affected MCLKDIV2/MCLKDIV4 configuration, the period was approximately 500 µs:

The issue was therefore reproduced in separate projects and does not appear to depen d on application-level interaction between the timer and other peripherals.

Main question

Could you please clarify whether this behavior is expected or whether is expected and what is a proper was to calculate timgx parameter configuration with LFCLK clock source

Best regards,
Danylo Plotskykh

ti_ccs_projects.zip

MSPM0G3519-Q1: MATHACL compiler support?

HS FAE Germany — Wed, 23 Sep 2026 12:29:05 GMT

Part Number: MSPM0G3519-Q1

Hi,
is automatic compiler support for the MSPM0 MATHACL module offered?
Eg:
result = a * b;
will the compiler automatically make use of the MATHACL hardware accelerator, or will we need to explicitly use the MATHACL API, for example:
result = MATHACL_DoMultiplication(a, b);
to benefit from the hardware acceleration?

Regards, Holger

AM62A1-Q1: Questions about TRNG on TI AM62A12

Zhang Liang — Wed, 23 Sep 2026 12:07:50 GMT

Part Number: AM62A1-Q1

Hello,

We received the above requirements from our customer. Please help confirm whether the True Random Number Generator (TRNG) of TI AM62A12 meets these requirements:

Which standard and version does this random number generator comply with? AIS20/31 A proposal for: Functionality classes for random number generators, Ver2.0 AIS20/31 A proposal for: Functionality classes for random number generators, Ver3.0
Does it meet the following content from the above standard? When using a true random number generator, the requirements of PTG.2 or PTG.3 of the RNG class in document AIS20/31 Ver2.0 or Ver3.0 shall be met.
Does it satisfy the following requirements? (1) When using the true random number generator described in document AIS20/31 Ver2.0, it shall pass Standard Statistical Tests in document AIS20/31 Ver2.0. Test Procedure A and Test Procedure B in document AIS20/31 Ver2.0 should be followed. (2) When using the true random number generator in document AIS20/31 Ver3.0, it shall pass the Black Box Test Suite in document AIS20/31 Ver3.0.
Does it satisfy the following requirements? (1) When using the true random number generator in document AIS20/31 Ver2.0, the Online Test in document AIS20/31 Ver2.0 shall be implemented. (2) When using the true random number generator in document AIS20/31 Ver3.0, the Online Test in document AIS20/31 Ver3.0 shall be implemented.

Could you also provide the related compliance statement or test evidence if available?

AM2612: EtherCAT evaluation stack vs SSC stack in AM261x Industrail communications SDK

Robert Huang — Wed, 23 Sep 2026 11:42:33 GMT

Part Number: AM2612

Hi experts,

There are 2 EtherCAT SubDevice demos, (1) one is using evaluation stacks (or called TI integrated stack) and (2) the other is using SSC stack in AM261x Industrail communications SDK. For evaluation stacks, they will run for 1 hour only if SSC library is not built up. For this case, when I build the example project, the error shown "[0]error #10008-D: cannot find file "ethercat_subdevice_bkhf_ssc.am261x_lp.r5f.ti-arm-clang.release.lib"", which seems we still need to have beckhoff library (SSC library). Could you please help how to solve this issue? Note: The imported project name is 'ethercat_subdevice_cia402_demo_am261x-lp_r5fss0-0_freertos_ti-arm-clang'

If we take option (1) and build up SSC library in advance, whic is unlimited TI integrated stack, what is the benefit compared to SSC library? What 's your suggestion for development EtherCAT SubDevice?

BR, Robert Huang

MSPM0G3507: CAN based FBL (bootloader) for MSPM0

Aditya Jethava — Wed, 23 Sep 2026 09:48:40 GMT

Part Number: MSPM0G3507

Hello TI Team,

We are currently working on an automotive ECU project using the MSPM0 [MSPM0G3507] controller.

We require a bootloader solution to perform application firmware updates over CAN. Could you please provide a demo/reference implementation for a CAN-based bootloader for the MSPM0 family, if available?

Our preliminary requirements are:

MCU: MSPM0 [MSPM0G3507]
Interface: CAN
Flashing protocol: [UDS/ISO-TP or proprietary CAN protocol]
Bootloader should support Flash erase and programming
Bootloader-to-application jump
Recovery/handling of interrupted firmware updates
Development environment: [CCS] with MSPM0 SDK [ 2.10.00.04]

AM5728: Am5728 eMMC boot issue

Hanmant Gaikwad — Tue, 22 Sep 2026 16:12:24 GMT

Part Number: AM5728

Hello TI Team,

We are using a custom AM5728 board. eMMC boot works with U-Boot 2016, but with our newer U-Boot build, SPL fails to load "u-boot.img".

The following log appears during boot:

U-Boot SPL 2026.07-dirty (Sep 22 2026 - 20:01:53 +0530)

DRA752-GP ES2.0

Trying to boot from MMC2_2

Loading Environment from FAT... Card did not respond to voltage select! : [error code cropped]

** Bad device specification mmc 0 **

Partition 1 invalid on device 1

spl_register_fat_device: fat register err - -1

spl_load_image_fat: error reading image u-boot.img, err - -1

spl: no partition table found

Error: -1

SPL: Unsupported Boot Device!

SPL: failed to boot from all boot devices

### ERROR ### Please RESET the board ###

Currently it's boot mode is 2

Could you please help me with this.

Which SPL configuration, device-tree, or MMC initialization changes should we check when migrating from U-Boot 2016?

The same board successfully boots from eMMC with the older U-Boot.

Thank you.

AM62A7-Q1: Emmc initialization issue and brick

Tudor-Cristian Morosanu — Tue, 22 Sep 2026 13:58:55 GMT

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62A74, SK-AM62A-LP

We are using TI AM62A74AUMSI-Q1 and Samsung KLM8G1GEUF-B04x eMMC. We are using TI PSDK version 11.2.Issue appears out of nowhere and renders the emmc completely unusable. During normal boot, SBL code does not even get loaded(presumably due to failure to access eMMC). In order to debug and get more info, we are booting into U-Boot using DFU mode. There, when trying to interact with the emmc we get back "Card did not respond to voltage select! -110". A similar behavior is observed also in Linux SAK where polling the mmc returns "card stuck being busy!". Also the QNX emmc driver devb-sdmmc-am65x fails to start and reports a similar issue.This issue does not seem to be related to software necessarily as tested, working software fails with the same issue. This issue randomly appears only on some targets(we have same HW-iteration boards, some failing, some working)Hardware team assures that electrically, signals are intact and the RST lines being the correct value.

Adding multiple prints in "mmc info" call, I was able to read the OCR register as being: 0100 0000 1111 1111 1000 0000 1000 0000

which seems correct, apart from bit 31 remaining stuck at 0, which seems to throw the resulting TIMEOUT error.

Testing for emmc health on a working target(same HW iteration as one of the failing ones, about the same usage by developers, same age of abround 2 months) we get both EXT_CSD registers 268 and 269 as being 0x01, so we are sceptical about this being a lifecycle end of the emmc problem.

Please provide your input regarding this issue, could this be caused by a HW/SW problem from TI's side?

AM2434: AM243x Launchpad ECAP sysconfig issues

Adam Hunter — Tue, 22 Sep 2026 13:49:19 GMT

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

In the MCU SDK 12.0.0 driver examples there is a loopback example for ECAP.

In the sysconfig for ECAP it only gives me an option to use pin MCAN1_RX or TX for ECAP1 & ECAP2.

However in the example it uses pin GPMC0_GP3, which actually links to EHPWM0 Channel A when i enable that in Sysconfig.

My question really is, is there any pins on the launchpad that map to ECAP which i can use inside of the module?

I can't seem to find any evidence of this working or any other examples

Thanks in Advance.

F29H859TU-Q1: the function safety

Jenney Ni — Tue, 22 Sep 2026 12:10:13 GMT

Part Number: F29H859TU-Q1

Hi all,

Do we have the example of ECC,lockstep and FLASH ECC? Do we have any document which describe it? I have the safety manual, but I only found an introduction to the principle, without any API or example documentation.

Regards,

Jenney

MSPM33C321A-Q1: Jlink/Jflash support

Fengyu Leng — Tue, 22 Sep 2026 11:19:59 GMT

Part Number: MSPM33C321A-Q1

Hi TI expert,

My customer would like to develope M33. We have tried that V9.44 doesn't work. Could you please help share how to configure Jlink and any Jlink version limiation? Thanks.

BR,

Fengyu

TDA4VH-Q1: Process two 4k@60 videos

Jithesh R — Tue, 22 Sep 2026 10:23:45 GMT

Part Number: TDA4VH-Q1

Need design help in designing a module that takes two 4k@60 videos, processes and provide a single 4k@60 video output.

AM2434: PROFINET Device stack: three application callbacks are bound by hardcoded symbol name instead of the documented callback registration API (no public prototypes)

Vit Triska — Tue, 22 Sep 2026 09:02:18 GMT

Part Number: AM2434

SDK: ind_comms_sdk_am243x_2026_00_00_06
Device: AM243x (R5F)
Library: profinetiodevice.am243x.r5f.ti-arm-clang.release.lib
Example: profinet_device_demo

The precompiled PROFINET Device stack requires three application functions to be resolved by fixed symbol name at link time, rather than through the documented callback mechanism (PN_API_IOD_Callbacks_t).

The nm shows the following undefined symbols that must be provided by the application:
APP_pruInit()
APP_HW_BOARD_INFO_read()
APP_HW_BOARD_INFO_getMacInfo()

These functions are neither declared in any public stack header nor documented in the API guide. As a result, applications must reverse-engineer prototypes and data structures that are effectively part of the library ABI. This appears to be a library design issue, not only a documentation gap.

Concerns
- No public declarations. The functions only appear in SDK example sources, not in public stack headers.
- Hard dependency on symbol names. Applications cannot rename, wrap, or abstract these interfaces.
- Inconsistent architecture. All other application hooks are provided through the documented callback registration mechanism.

Question

Is the fixed-symbol binding intentional, or is it a legacy artifact from the time when the BSP adaptation layer was distributed as source code?

Requested improvement

Please, migrate these hooks to the existing callback mechanism (for example, by extending PN_API_IOD_Callbacks_t or rather adding a dedicated registration API). This would remove the symbol-name dependency and provide compile-time prototype checking.

At minimum, please:
- Declare all three functions in a public stack-owned header.
- Move APP_HW_BOARD_INFO_SMAC_Addr_t (or an equivalent stack-owned type) into that header.
- Document the type, field semantics, MAC address usage, and per-port MAC derivation.
- Document the entire mechanism in the API Guide.

Thank you in advance for the clarification.

Regards, Vit

AM13E23019: SVD Register Definitions Files

Jan Bock — Tue, 22 Sep 2026 08:54:42 GMT

Part Number: AM13E23019

Hello Team,

My customer looks for the SVD Register Definitions Files. Can we provide them?

Jan

TIDM-1000: Input Current Zero-Crossing Distortion Causing Low-Frequency CE102 Noise Issue

Vignesh m — Mon, 21 Sep 2026 14:59:39 GMT

Part Number: TIDM-1000

Dear Team,

I am facing a CE102 noise issue at 10 kHz under the Build 4 test condition.

Filter Details:

Dual-stage Pi filter 169uH, 1uF
Input Voltage Vin: 95Vac Vout: 320Vdc

Waveform Channels:

Yellow: R-phase Boost Current
Green: Vout
Orange: R-phase Input Current

We are observing input current distortion in the 2 A to 4 A load region. Kindly suggest potential solutions to resolve this issue.

Best regards,

Vignesh

AM2634-Q1: debug the HS-SE device

Jenney Ni — Mon, 21 Sep 2026 14:18:24 GMT

Part Number: AM2634-Q1
Other Parts Discussed in Thread: UNIFLASH

Hi all,

I will describe the status of a faulty component. Could you provide some debugging ideas? Thanks so much.

AM2634COKFHMZCZRQ1: This is a zero-kilometer car right off the factory assembly line. The entire OBC (On-Board Charger) module is not working. It has not been removed from the vehicle yet, but it will be disassembled later. What troubleshooting or inspection work can be performed right now under the current conditions?
HS-SE State & Blown JTAG: The device is in the HS-SE (High Security - Security Enforced) state, and the JTAG interface has been blown (fused). Only the UART port is available, but currently, the SBL (Secondary Bootloader) fails to start normally.
Root Cause Verification: Is there a way to confirm whether the SBL failed to boot due to an HSM ROM secure verification failure of the SBL image, or if it was caused by some other reasons?
Image Readback via UART: It seems that sbl_uart_uniflash can only write new images to the flash but cannot read back the current image from the device. Is there any method to read back the existing image from the device via the UART port?

Regards,

Jenney

AM263P4: PBIST hangs in SDL_PBIST_runTest() when application is booted from OSPI

Gokul A Nair — Mon, 21 Sep 2026 13:28:02 GMT

Part Number: AM263P4

Hi Team,

I am facing an issue while running PBIST example project imported from mcu+sdk on AM263Px.

The PBIST application works as expected when the application is loaded and executed through CCS Debug mode. However, when the same application is flashed and booted through OSPI using SBL, the execution gets stuck inside the following function: SDL_PBIST_runTest().

The issue occurs while running the TOP PBIST failure insertion test.
The same PBIST test runs successfully when the application is executed through CCS Debug mode.

Observed behavior:
CCS Debug mode: PBIST failure insertion test and normal PBIST test complete successfully.
OSPI boot mode: Execution gets stuck inside SDL_PBIST_runTest() during the TOP PBIST failure insertion test.

Sharing the logs in both the cases:
pbist_debug_log.txt pbist_ospi_log.txt

Could you please help resolving this issue.

MSPM33C321A: Error with SPI Clock (BUSCLK)

Keith Barkley — Mon, 21 Sep 2026 13:09:02 GMT

Part Number: MSPM33C321A
Other Parts Discussed in Thread: SYSCONFIG

I am trying to copy another project I have that works fine with the 160 MHz clock. I think I have the clock-tree and sysctl settings the same, but I get a sysconfig conflict: "Clock Source BUSCLK not properly initialized in SYSCTL"

However, I see no mention of BUSCLK in SYSCTL and the TRM only mentions BUSCLK as a source, not setting it in the clock section.

How do I fix this?

(Is the name BUSCLK being deprecated?)

AM263P4-Q1: Uniflash Tool Issue while flashing the image

Shilpa G — Mon, 21 Sep 2026 12:55:46 GMT

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: UNIFLASH

Hi TI Team,

We are working on flashing the application image via Uniflash tool by using the JTAG debugger, while loading the image we are facing the below issue as attached.

where as it is working when we use SBL JTAG Uniflash example project in debug mode from CCS studio.

We are using
Uniflash Tool (Version: 9.6.0.5764)
controller - AM263Px F-variant.

Thanks,
Shilpa G

AM2434: AM2434 + MT25QL128: Sporadic OSPI NOR Flash corruption after many reboots

Martin Gschwendner — Mon, 21 Sep 2026 12:19:33 GMT

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi,

we are using a custom board with AM2434 and Micron MT25QL128ABB8E12 OSPI NOR Flash.

The system boots and runs reliably. However, after many reboot cycles, we occasionally observe flash corruption which eventually prevents the bootloader from starting.

Observations:

Corruption occurs very sporadically (after many reboots, 10 .. 1000).
The affected location is not always the same (in the first sector, SBL).
Only a single 64-bit aligned entry is modified.
The modification is persistent and visible in a flash readback.
Only 1 → 0 bit transitions are observed.
No erase pattern is visible (no 0xFF regions, no sector damage).
The bootloader image itself gets corrupted and the device stops booting.
We currently suspect that the corruption happens during the boot phase (SBL + Application bootup).

Questions:

Does Flash_EnableDacModeFxn() only configure the OSPI controller DAC (memory mapped) mode, or can it also access/configure the flash device itself?
For a custom flash configuration, are there any known requirements regarding Flash_EnableDacModeFxn() for Micron MT25QL128 devices?
Has anyone seen sporadic single-word (64-bit) programming events during reboot/reset sequences on AM243x devices?
Are there known OSPI controller, reset sequencing, or power-down corner cases that could lead to an unintended flash program operation?

Since only 1→0 transitions occur, this looks more like an unexpected program command than a read/DAC/PHY issue.

Any hints or similar experiences would be appreciated.

Thanks!