https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1607221/am6422-freertos-cpsw-switch-1588/6296081Fri, 03 Apr 2026 16:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:81818ce4-a91f-4505-9973-c8c8da378baeTeja RowthuHi, We didn&#39;t observe this specific behaviour in our boards. But let us recheck this and get back to you about this topic. Regarding the phase match, the expectation is that the user would have to start the two boards with in the time frame of 1 second. We can update this to be upto few seconds of difference. This can be found in the genf correction patch provided earlier, where we set the genfArgs.compare input based on currentTsVal time stamp. By adjusting the calculated value, the boards can be made to start outputing the signal at multiples of 5 or 10 seconds, so that there is enough time to start both examples within that time frame. An easier and preferred method is to flash the example in ospi flash memory, and booting from ospi mode, and powering on both boards simultaneously. This ensures phase match on output signals. Thanks and regards, Teja.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1627797/am2431-am243x-cpts-module-and-time-sync-router-questions/6296067Fri, 03 Apr 2026 15:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a1fdf8ee-27c8-4eaf-b445-22397cded006Teja RowthuHi Matt, Please let me run this in our test bench and try to identify the issue. 22us delay is on the higher side than expected. I assume some critical sections are getting executed in the periodic tasks which are causing this issue. Please let me reproduce this for further analysis. Since Friday is TI india holiday, this activity will be taken up on Monday. Thanks and regards, Teja.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633115/tms320f280039c-bootloader-devlopment/6296000Fri, 03 Apr 2026 13:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1db7206f-2156-4363-bcd8-06c457dcdea4Matt KukuckaHello, What issues are you specifically encountering? Please refer to this FAQ for general reference: [FAQ] C2000 Bootloading Design Considerations Best, Matthttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633013/lp-am263p-expanding-ocram-causes-program-flash-from-ccs-to-fail/6295946Fri, 03 Apr 2026 11:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:981b307e-ad7e-4fa9-a705-b40ac16069e5Aswin SankarHi, By default it seems to be 0x3F. There is a possibility that your gel files are not updated. Can you please update CCS to latest version and then do check for updates? ... Thanks &amp; Regards, Aswinhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633249/am263p4-am263p4-r5f-core-mode-switching-dual-core-lockstep-with-pbist-and-ccm-soc_rcmgetcorefout-assertionFri, 03 Apr 2026 11:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7a52bcd0-8814-4f3e-97a4-14a31f4b744bSaravanan PPart Number: AM263P4 Hi Team, I am working on the AM263P4-CC device and currently integrating PBIST and CCM as part of the SBL for safety diagnostics during boo . I need clarification on core mode configuration, sequencing , and I am also encountering an assertion related to clock configuration. System Details Device: AM263P4-CC Core: R5FSS0-0 SDK Version: MCU+ SDK (11.01.00.19) Toolchain: TI ARM Clang (via CCS) Current Design Approach PBIST is executed during early boot as part of SBL. CCM is planned to be enabled after PBIST completion, still within SBL. My understanding is: PBIST may require Dual-Core mode CCM requires Lockstep mode Based on this, the intended flow is: Start in Dual-Core mode Execute PBIST Switch to Lockstep mode Enable CCM Continue boot / handoff to application Queries 1. Core Mode Switching in SBL Is it supported to switch the R5F core mode from Dual-Core to Lockstep mode within the same boot cycle (inside SBL) ? If yes: What is the recommended sequence? Is a warm reset or full reset required? Can this transition be done via software (RCM registers), or is it only configurable at boot/reset? 2. PBIST Dependency on Core Mode Is Dual-Core mode mandatory for executing PBIST? Can PBIST be executed when the core is already configured in Lockstep mode ? 3. CCM Initialization Requirements Does CCM require the core to be in Lockstep mode prior to initialization , or can it be enabled after a runtime mode switch? 4. SBL Execution Constraints When executing PBIST and CCM within SBL: Are there any constraints related to memory usage, isolation, or core activity? Are there recommended sequencing guidelines for safety diagnostics in SBL? 5. SOC_rcmGetCoreFout Assertion Issue I am encountering the following assertion during early initialization when executing the PBIST example MUC+SDK code in both Debug and Release mode: [Cortex_R5_0] ASSERT: 0.1259s: soc/am263px/soc_rcm.c:SOC_rcmGetCoreFout:1588: FOut != 0 failed !!! It appears that FOut is returning 0. Questions: Could this be due to incomplete clock/PLL initialization? What are the required steps before calling SOC_rcmGetCoreFout() ? I&#39;m attaching the snapshot below for your reference: 6. Reference Example Request Is there any TI reference example demonstrating: PBIST execution CCM enablement Within a single SBL/boot flow on AM263Px? Your assitance is greatly appreciated.AM263P4Aerospace &amp; Defensehttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633229/uniflash-regarding-verification-methods-using-the-uniflash-cliFri, 03 Apr 2026 09:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f2dd4561-fee2-4822-bb23-dc9ce7641cbaATSUKI IMADAPart Number: UNIFLASH Other Parts Discussed in Thread: AM263P4 , We are currently developing a custom board using the AM263P4 and are in the process of setting up a mass production line. Until now, since we were in the development phase, we have been using the GUI version of UniFlash. However, the GUI version does not provide a verification function after programming. During our investigation, we learned from the Quick Start Guide that the CLI version supports verification after programming. Based on this information, we converted the project we had been using into a CLI-based workflow and executed it. As a result, the following output was displayed: info: Cortex_R5_0: Program verification successful for Multiple Files Success From this message, we understand that the verification has been completed successfully. However, we would like to know how the verification is actually performed , and we would appreciate it if you could provide a more detailed explanation of the verification mechanism. The details of our environment and the command used are as follows: MCU : AM263P4 UniFlash Version : 9.3.0.5401 Command used: dslite --mode flash -c user_files/configs/AM263Px_ZCZ_C.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad=&quot;No verification&quot; -e -f -v &quot;user_files/images/xxx.tiimage,0x60000000&quot; &quot;user_files/images/yyy.appimage,0x60081000&quot; ( Note: xxx and yyy represent the actual program file names. ) In addition, although it may be unrelated to the above, we sometimes observe behavior in which the program does not seem to be written correctly unless the programming operation is performed multiple times, both when using the GUI and the CLI. Are there any recommended methods to identify the root cause of this issue, or known solutions to resolve it? Thank you very much for your support.UniFlashAM263P4https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1632346/am2434-am243x-ddr-ecc-test-error/6295920Fri, 03 Apr 2026 09:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:817d8add-1eae-4967-bbcc-93b5eb3e451fTony TangHi Nihar, Customer changed it to &lt;&lt;3 and get right result. Please help to confirm, if it is right, suggest file a jira to update in next release.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1631460/am2434-ti-s-i2c-driver-gets-stuck-in-some-situations/6295902Fri, 03 Apr 2026 09:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0a0acdaf-5884-4448-84dd-9e421ba3ede6PetaMy first approach was the HLD i2c driver in callback mode. With that setting I ran into the issue the first time. The issue occurs as soon as I enable the i2c interrupts in the sysconfig. Then it doesn&#39;t care if the transfer mode is callback or blocking. In both cases interrupts are used. Only if I disable the i2c interrupts in sysconfig I cannot observe the issue. But since I don&#39;t want to block code execution, this is no option for me. What I miss is an API service that polls if an i2c transfer is done, without blocking or interrupts. Btw: Were you able to reproduce my example?https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633187/am62p-how-to-add-avb-function-into-sdkFri, 03 Apr 2026 08:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9db53cf3-14c8-4187-b6b4-42f7f7f1c7eapengfei suiPart Number: AM62P Hi Ti we want use Audio/Video Bridging (AVB) , https://tsn.readthedocs.io/avb.html How to use AVB function at AM62P ? ThanksInfotainment &amp; ClusterAM62Phttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633185/lp-am261-lp-am261-secure-boot-supportFri, 03 Apr 2026 07:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:580ad46f-ecf2-4f15-9556-068666055c7dDP14Part Number: LP-AM261 Hi, I want to implement the secure boot functionality (device should boot only with valid signed application firmware image). For this I have generated the public-private key pair as follows: # Generate RSA-2048 signing key (store in secure location) openssl genrsa -out /secure/keys/prod_signing_key.pem 2048 # Generate AES-256 encryption key (optional) openssl rand -hex 32 &gt; /secure/keys/prod_encryption_key.pem #Extract public key from the private key openssl rsa -in prod_signing_key.pem -pubout -out publickey.pem Added the private key paths and secure boot related configurations as follows in the makefile_ccs_bootimage_gen file: # Default secure boot/signing settings (can be overridden through command line) DEVICE_TYPE ?= HS ENC_ENABLED ?= no RSASSAPSS_ENABLED ?= no APP_SIGNING_KEY ?= $(abspath keys/private_key.pem) APP_SIGNING_KEY_KEYRING_ID ?= 0 APP_SIGNING_HASH_ALGO ?= sha256 APP_ENCRYPTION_KEY ?= $(abspath keys/private_encryption_key.pem) APP_ENCRYPTION_KEY_KEYRING_ID ?= 0 KD_SALT ?= 0x12345678 And build the firmware using the following commad make -f makefile_ccs_bootimage_gen OUTNAME=gpio_input_interrupt PROFILE=Release MCU_PLUS_SDK_PATH=C:/ti/mcu_plus_sdk_am261x_26_00_00_01 CG_TOOL_ROOT=C:/ti/ccs2050/ccs/tools/compiler/ti-cgt-armllvm_4.0.4.LTS CCS_INSTALL_DIR=C:\ti\ccs2050\ccs\ CCS_IDE_MODE=desktop DEVICE=am261x DEVICE_TYPE=HS These steps generated the secure .mcelf.hs image. Are the above mentioned stepts correct for secure application image generation? If no, provide me with the correct way. If yes, I want to flash this firmware on the device. But my question is how the device will know the public key for validating the firmware? Do I need to provide the public key in SBL? If yes, please explain, how? If no, provide the correct way for this. Because what I understood from the documentation is, 1. On AM261x, the SBL does NOT store the public key and does NOT perform signature verification of the application image. 2. Verification is done by the HSM ROM. It validates the SBL itself, not the application. The ROM verifies: The X.509 certificate The RSA‑4096 signature The SHA‑512 integrity hash Optional AES‑256 encryption 3. Public key is stored inside the X.509 certificate. But, &quot;How to store Public key inside the X.509 certificate?&quot; 4. Only after SBL authentication, execution proceed 5. After boot, SBL may optionally validate the application, but this is not part of TI’s secure boot ROM flow. 6. If I want application-level authentication, I have to 1. Embedding your own public key into SBL 2. Signing the application image (similar to SBL) 3. Having SBL verify the signature before loading the app Is my understanding correct? If no, please correct me. If yes, kindly clarify my doubts listed below. 1. For application-level authentication, how to embedd the public key into SBL? 2. What changed I shall need to do for having SBL to verify the secure application image before loading?LP-AM261https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633023/am6411-am64x-evm-failure-to-verify-connection-to-xds110-usb-debug-probe/6295821Fri, 03 Apr 2026 07:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:078c8c01-9a7a-4e99-8951-286f132895adTushar ThakurIt looks like your SOC is not initialized properly. Please initialize the SOC via SBL binaries. Please refer EVM_FLASH_SOC_INIT for details. Regards, Tusharhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633153/am263p2-am263p-ethercat-master-development-pru-vs-r5f/6295778Fri, 03 Apr 2026 06:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:589ceb01-da96-4fbb-9c06-c3cc9a25ea8bNilabh AnandHi G, Thank you for your query. The EtherCAT master does not need a specific networking peripheral like ICSS. EThercat master and EThercat slave fundamentally differ at the MAC level interface, because even your Windows PC can act as a master, as long as it can support sending packets out of the Ethernet interface. So that means you should use the CPSW interface to implement the EtherCAT master. I can give you one example: Let&#39;s take the SOEM master stack as an example. The SOEM stack only needs a network socket i.e a way to generate an Ethernet packet with a specified Eth Tag, which can be done using CPSW. - Implement an OS abstraction layer compatible with FreeRTOS - Develop a network interface adapter for CPSW - Implement necessary socket/packet handling functions - Port SOEM&#39;s low-level Ethernet access functions to use CPSW - Adapt timing functions to work with AM263Px timers - Implement proper interrupt handling for packet reception - Create a project structure for the EtherCAT master application - Implement initialization sequence for CPSW and SOEM - Add configuration options for EtherCAT master behavior - Implement a state machine for EtherCAT communication public.acontis.com/.../os_freertos.htmlhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633153/am263p2-am263p-ethercat-master-development-pru-vs-r5fFri, 03 Apr 2026 06:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ac00fae7-acaa-4c9c-9109-e737372e847fG GypsoPart Number: AM263P2 Dear TI Engineer, I am an engineer developing an EtherCAT Master on the AM263P. I am seeking your expert guidance due to critical roadblocks in the PRU firmware development. 1. Current Blockers Our core goal is to implement an EtherCAT Master using the AM263P. We face two major issues: 1) Example Mismatch: The PRU examples in the MCU+SDK handle standard Ethernet frames, not EtherCAT. Adapting them requires massive rework. 2) The existing PRU code is in Assembly, making modification, debugging, and maintenance extremely difficult. 2. Required Support (PRU Path) Please advise on the following: 1) Development Best Practices: Recommended workflow for integrating PRU firmware with the EtherCAT Master. 2) Alternative Resources: Does TI provide a pre-built PRU firmware for AM263P EtherCAT Master? If not, is there a C-language example or one requiring minimal changes? 3) Modification Guide: Key modules to modify in the existing Assembly examples and any official documentation to reduce debugging time. 3. Feasibility Study (R5F Only Path) We are also evaluating a solution without PRU: Performance Benchmark: If using one R5F for the Master and another for control logic, what is the minimum cycle time achievable with 32 slave nodes? 4.Current Resources TI AM263P launchPad, CCS 12.8.1,mcu_plus_sdk_am263px_10_02_00_15, ind_comms_sdk_am263px_10_02_00_22 The PRU example mentioned above is located at mcu_plus_sdk_am263px_10_02_00_15\source\networking\icss_emac, named dual_emac_am263px-lp_icss_m0_pru0_fw_ti-pru-cgt. Thank you for your time and support. Please let me know if you need further details. Best regardsAM263P2https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1632285/mspm0g3519-q1-mspm0g3519-q1-mcal_mspm0_00-02-05-00-gpt-does-not-generate-the-channel-id-as-a-define/6295704Fri, 03 Apr 2026 05:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e5d8403f-d2db-48ad-b2ed-0bb2e6314a17Helic ChiWhich EB version are you using? MSPM0 only supports EB 24.0.0 You can get it from ti.com If you are using EB 24, please guide me how to reproduce this issue.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633131/am2432-am2432-mspi---multicontroller-mode---cs-pin-toggling-unexpectedly-and-not-controllableFri, 03 Apr 2026 04:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:312aa8ae-6b54-4611-ae9e-441f477a5e1fNilesh ParmarPart Number: AM2432 Hello TI Team, As per our requirements, we have to use two chip select pins of MSPI which can be controlled by the user based on their requirements. For achieving two chip select requirements, mspi shall be configured in multi-controller mode instead of single. When we configure mspi in multic-ontroller mode, it does not allow us to controll the chips select (TRUE = CS is de-asseted automatically at the end of the transaction and FALSE = If user wants to chain more transfers under one CS pulse). Based on our observation, CS pin is automatically de-asseted after 1 byte transfer and observed glitches in transfer. Below configurations are for multi-controller mode of MSPI . In Single control mode, we are able to control the chip select and have not observe any glitch. In Multi control mode, we are not able to control the chip select for more transaction, it automatically de-asserted after transfering 1 byte data which result in communication failure with the slave device and observed the glitches during it. I have captured signals of single-controller mode and multi-controller mode. Kindly analyse it and provide the measures. MSIP_SALEAE_SIGNLES_CAPTURE.zip Best regards, Nilesh V ParmarAM2432https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1632346/am2434-am243x-ddr-ecc-test-error/6295664Fri, 03 Apr 2026 03:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0cd18c69-9f61-4c53-9bd0-da64224fe781liang luoI think the reason is that there is a bug here: each bit in the register corresponds to 8 bytes, so it should be &quot;* 8&quot; (or &quot;&lt;&lt; 3u&quot;) instead of &quot;&lt;&lt; 1u&quot;.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1633115/tms320f280039c-bootloader-devlopmentFri, 03 Apr 2026 03:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ecdff606-5c44-4224-84e3-9e84f754b565Vikas KumarPart Number: TMS320F280039C we are facing issue during devlopmement of bootloadoaer. kindly supportTMS320F280039CSoftware-defined vehiclehttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1629647/am625-custom-board-based-on-am625x-cpu-does-not-working/6295649Fri, 03 Apr 2026 02:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9a5aa0bb-d1d2-4f2d-ae41-dfa397d28af8Kallikuppa SreenivasaHello Jeong-Seon Lee Thank you. The issue being observed is the MCU_PORz input goes high much before the supplies ramp. This may likely not initialize the internal circuits as expected. The MCU_PORz is generated from and external logic. After all the supplies ramp, can you force the MCU_PORz low and release. This is not a recommended practice since the output shorts to ground. This is recommended as a quick check. Can you please give a try. Regards, Sreenivasahttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1620644/lp-mspm0g3507-lp-mspm0g3507-nack-errors-on-the-mcan-bus/6295635Fri, 03 Apr 2026 02:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2288b620-3531-4651-95ca-710f96a9c002Helic ChiGlad to hear your issue resolved~ thanks for the feedback~https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1629647/am625-custom-board-based-on-am625x-cpu-does-not-working/6295632Fri, 03 Apr 2026 02:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bd843e8a-a36e-42e6-9585-03c94f2ea064Jeong-Seon LeeThis is the 25M Clock measured with an X10 probe. Is there anything in particular that needs to be observed?