https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1669314/mspm0g3519-crc16-not-working-for-mspm0/6448048Wed, 12 Aug 2026 07:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ef8c98b-ca62-4989-bf4b-fdddcaa5384eJasper LiHello, Could you please share your current configuration parameters so I can verify the settings? Specifically, I&#39;d like to confirm the following: Seed is set to 0x0000 BitOrder is set to Reversed ByteOrder is set to Big Endian Additionally, could you let me know whether the data length of your Flash calculation region is an odd or even number of bytes? This will help narrow down the issue.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672340/am2434-r5fssx-core-re-configuration-with-sdk/6448009Wed, 12 Aug 2026 06:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0e712acb-4494-45fc-9791-ba5212b5592eSergej SergeyukHello, Meet. At the first: thank you for clarification of the Single-Core and LockStep. Next: I need to double the TCM memory. That is what i&#39;m looking for. Does SDK support that?https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672565/tms570lc4357-f021-api-read-issues-after-writingWed, 12 Aug 2026 06:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:de5ed59c-2347-456a-9312-14aff570a7f1shuo liuPart Number: TMS570LC4357 Hi, Dear Ti Team After using the F021 API to write data to the on-chip flash, when I try to read the data using the F021 API or by retrieving the address, I find that the data is still the same as before. This seems to be a caching issue. How can I resolve this problem? It’s worth noting that I don’t want to disable the cache.TMS570LC4357Applianceshttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672340/am2434-r5fssx-core-re-configuration-with-sdk/6447981Wed, 12 Aug 2026 06:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1877d1e9-625d-4a82-b659-14ec7d35ba24Meet Thakar[quote userid=&quot;84802&quot; url=&quot;~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672340/am2434-r5fssx-core-re-configuration-with-sdk/6447358&quot;]Is my expectation that tthe TCM memories are doubled when cluster in the &quot;single-core&quot; mode correct? [/quote] An R5F cluster does support the single-core mode (but this is not the same as lockstep mode), in which CPU0 is the only operating core but can use CPU1&#39;s TCMs as well, so this understanding is correct. By default R5 cores are configured in split mode and SBL doesn&#39;t configure them to single-core mode, so there is no need for you to change any configuration for this.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672485/am6442-am64x-am6442-flashcp-times-out-writing-to-ospi-nor-flash-from-linux-works-fine-from-u-boot/6447948Wed, 12 Aug 2026 06:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c26bb0b0-93f8-49f9-8edc-b7e6de0ce45eVinuchandran A VHi Srikanth, Thanks for the detailed writeup. Given that U-Boot (which does its own OSPI timing setup) always succeeds, and Phytec&#39;s newer 6.12.79-based kernel works with the same 128KB eraseblock config, I&#39;d look closely at your Q4. The PHY/DLL calibration code present in TI&#39;s linux-phytec-ti 6.12.35 tree but absent from your 6.12.8 base. That&#39;s a strong candidate for the remaining gap. As an initial step, can you try reducing the OSPI clock via DT (spi-max-frequency)? Also, please do a diff of the full driver, not just the two cherry-picks. From the same Phytec 6.12.79 tree that works and diff it against your 6.12.8+backports tree. Regards, Vinuhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672268/tms570lc4357-ep-unable-to-see-data-in-mibspi1-tx-ram-when-operating-in-dma-mode/6447931Wed, 12 Aug 2026 06:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e9508aea-1513-4ef2-8776-8840cfa0963ajagadish gundavarapuHi Chaya, Before i went through your code i would suggest you verify some tested DMA examples from TI end. Here are they: In below FAQ you can find several examples: (+) [FAQ] TMS570LC4357: Examples and Demos for Hercules Controllers (E.g. TMS570x, RM57x and RM46x etc) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums Also refer below e2e&#39;s: (+) TMS570LS3137: MIBSPI + DMA - First transaction all 0&#39;s - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums (+) TMS570LC4357-EP: TMS570LC4357 MibSPI DMA Transfer Limit and Large Data (12KB) Transmission Clarification - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums -- Thanks &amp; regards, Jagadish.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1670702/mspm0g3519-q1-mspm0g3519-issues-with-mcal_mspm0_01-00-00-00/6447917Wed, 12 Aug 2026 06:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:afc610fd-fea5-42aa-aa20-2d102a24e68fMarkus RiglingI am not able to open the Marquardt E2E.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1671518/rm48l952-rm48l952-emif-asynchronous-interface-clarification-of-the-td-parameter-used-in-section-17-4-2-2-of-the-trm/6447904Wed, 12 Aug 2026 05:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4fc4acb5-87f8-4c17-8780-0e937e038f6bjagadish gundavarapuHi QJ Wang This is a follow-up of your one of the previous threads, hopefully you could help customer here. -- Thanks &amp; regards, Jagadish.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1671957/tms570lc4357-query-regarding-functional-safety-support-for-ti-compilers-for-hercules-mcus/6447841Wed, 12 Aug 2026 05:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6e23f407-c495-498c-a15d-da73e67dbbb5MOHAMED ASHEEQHi Jagadish, Thank you for sharing the CQKIT details. We are preparing the compiler qualification document for our customer, and I have one clarification. From the documents, I understand that the SafeTI Compiler Qualification Kit has been assessed by T&#220;V. Does this assessment also apply to the TI ARM C/C++ Compiler (20.2.x LTS), or only to the Qualification Kit? For our customer documentation, what is the correct statement to use? The TI ARM C/C++ Compiler is qualified using the T&#220;V-assessed SafeTI Compiler Qualification Kit. Or, the TI ARM C/C++ Compiler is T&#220;V certified/assessed. If there is an official document or certificate that clarifies this, could you please share it? Thank you.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1671479/tida-010090-tida-010090-heatsink-requirements-and-thermal-design-for-50-a-operation/6447801Wed, 12 Aug 2026 04:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:47fbc1c1-6bc9-4fee-ac03-af386b89b98dEthan Yu(SH)Hi Sunggyu, It is possible to achieve full load condition if a proper size of heatsink is selected. Placing heatsink directly on top with TIM can quickly evaluate the performance in stable lab environment. New version of the board can also be requested, please contact local FAE to initiate the support. Thanks, Ethanhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1669867/mspm0c1104-will-i-run-into-problems-if-i-have-the-supply-voltage-change-when-using-the-mspm0c1104/6447776Wed, 12 Aug 2026 03:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e318beb0-1646-438e-8e61-487d5c467f58Parker BondiHello Wyatt, I am not able to share new captured data as I&#39;m having another problem with my MCU at the moment that I am working through. But I do have a photo oh my multimeter showing that the voltage increased from 1.8V to 2.5V. I also have seen for sure that I am able to readback, but my only picture that I have using the logic analyzer was from when I first was working on this project which I show here where I am setting the sys vout to 2.5V by sending 0xB8 to register 0x06 of the BQ. The BQ has a 7-bit address of 0x6A so we see 0xD4 when writing. THe BQ acknowledges and then I follow up with a request to read the register. Early on in my development some weird things were happening but after figuring out that I seemed to need to provide voltage to the VIN pin of the BQ, anytime I tried to program it while I was doing so seemed to be successful. Any other suggestions / things for me to investigate would be greatly appreciated.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672095/arm-cgt-clang-generating-crc-table-with-linker---group-errors/6447760Wed, 12 Aug 2026 03:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1662cddd-cdf0-435c-9a3f-7d2c7d0686e3GregMPlease confirm if the issue is with TI Arm Clang or with TI ARM 20.2.7.LTS You cannot use the TI Arm Clang user guide for TI ARM 20.2.7.LTS. Please see below instead for supported features: https://www.ti.com/lit/ug/spnu118z/spnu118z.pdf?ts=1786504550925&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252Fdownload%252FARM-CGT%252F20.2.7.LTShttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672448/mspm0g1106-configuring-adc-not-available-via-sysconfig-tool/6447740Wed, 12 Aug 2026 02:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d077a327-c935-49fe-ad12-e4d2a6230a0cKyungjae LeeI see. I must have missed the section. Thank you for taking the time to clarify this. Best regards, Kyungjae Leehttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672448/mspm0g1106-configuring-adc-not-available-via-sysconfig-tool/6447737Wed, 12 Aug 2026 02:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:346c89fd-86bf-4622-80a8-196690367564Janz BaiIn the &quot;ADC Conversion Memory x Configuration&quot; module, it is in the sysconfig and I think it is very easy to find. Please check your sysconfig carefully. BR, Janz Baihttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672448/mspm0g1106-configuring-adc-not-available-via-sysconfig-tool/6447736Wed, 12 Aug 2026 02:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ba8c9890-5194-4527-97ce-6e71a91e7fb9Kyungjae LeeHi Janz, I appreciate you getting back to me. That is exactly what I was trying to do but I couldn&#39;t seem to find the way to change the channel through the sysconfig tool I&#39;m using. Where can I change it? My environment setting is: IDE: Code Composer Studio (Version: 12.7.1.00001) SDK: MSPM0 SDK (Version: 2.1.0.03) SysConfig: 1.19.0 Could it possibly be due to the SysConfig tool version? Thank you, Kyungjae Leehttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672448/mspm0g1106-configuring-adc-not-available-via-sysconfig-tool/6447725Wed, 12 Aug 2026 02:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:00efc842-7622-4c63-b2e2-897e58d075cdJanz BaiHello Kyungjae, Because PA14 is the ADC0_channel 12. In the sysconfig, you use the channel 0. Please change to use channel 12 in your sysconfig then you can use the PA14. BR, Janz Baihttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672485/am6442-am64x-am6442-flashcp-times-out-writing-to-ospi-nor-flash-from-linux-works-fine-from-u-bootWed, 12 Aug 2026 00:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:aacfa37f-708e-4625-8782-3c1ef65f8032Srikanth GurramPart Number: AM6442 Hi TI team, We are using the phyboard-electra-am64xx-2 with AM6442 SR2.0 HS-FS and Micron mt35xu512aba 64MB OSPI NOR flash. We are trying to flash bootloaders (tiboot3, tispl, u-boot) to OSPI from Linux as part of our production workflow but running into a consistent timeout. Hardware: Board: phyboard-electra-am64xx-2 SoC: AM6442 SR2.0 HS-FS OSPI Flash: Micron mt35xu512aba 64MB (JEDEC 0x2c5b1a) BSP: Phytec BSP-Yocto-Ampliphy-AM64x-PD25.2.0 Kernel: linux-phytec 6.12.8-phy7 What works: Flashing all three bootloaders from U-Boot using mtd commands works perfectly every time. mtd erase ospi.tispl load mmc 0:1 0x80000000 tispl.bin mtd write ospi.tispl 0x80000000 0 ${filesize} tiboot3 (488KB) also flashes successfully from Linux using flashcp. What fails: tispl (833KB) and u-boot (1.3MB) consistently time out from Linux. flash_erase /dev/mtd2 0 0 -- succeeds flashcp /boot/tispl.bin /dev/mtd2 -- fails Error: cadence-qspi fc40000.spi: Flash command execution timed out spi-nor spi0.0: operation failed with -110 While writing data to 0x000d0000-0x000d00a7 on /dev/mtd2: Connection timed out The timeout always occurs at exactly offset 0x000d0000 regardless of which tool we use (flashcp, dd, mtd_debug). This is not random -- it fails at the same offset every time. Kernel changes we have already applied: 1. cdns,read-delay = 2 in device tree (required for chip probe) 2. CQSPI_TIMEOUT_MS increased from 500ms to 30000ms 3. Removed SECT_4K from mt35xu512aba driver entry 4. CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n (changes eraseblock from 4KB to 128KB) 5. Backported Linux 6.12.54 patches: - spi: cadence-quadspi: Flush posted register writes before INDAC access (commit 29e0b471) - spi: cadence-quadspi: Flush posted register writes before DAC access (commit 1ad55767) 6. Added CQSPI_NEEDS_APB_AHB_HAZARD_WAR to am654_ospi platform data Current state after all fixes: Eraseblock size is now correctly 128KB matching the chip native sector size. flash_erase works correctly. flashcp write still times out at 0x000d0000. Observations: tiboot3 (488KB) writes successfully -- fits within first write chunk tispl (833KB) fails -- requires multiple write chunks, second chunk times out The Cadence QSPI indirect write completion interrupt appears to stop firing after the first successful write cycle Phytec BSP PD25.2.1 uses kernel 6.12.79 and their documentation shows flashcp working correctly with 128KB eraseblocks. We are on 6.12.8. Questions: 1. Is there a known issue with the Cadence QSPI indirect write completion interrupt on AM6442 that causes the second write chunk to time out? 2. Are there additional patches required beyond the 6.12.54 INDAC and DAC flush fixes for reliable OSPI writes on AM64x? 3. Does am654_ospi platform data need additional quirks beyond CQSPI_NEEDS_WR_DELAY for AM64x? 4. The TI linux-phytec-ti kernel (6.12.35) has full PHY calibration code (phy_setting, DLL registers 0xB4/0xB8/0xBC) that our kernel 6.12.8 does not have. Is PHY calibration required for reliable write operations on AM64x OSPI? 5. What is the recommended kernel version and configuration for reliable Linux-side OSPI NOR flash programming on AM6442? Any guidance would be greatly appreciated. We need to enable Linux-side OSPI flashing for our production workflow as U-Boot access will not be available at the factory after initial programming. Thank you. Srikanth Gurram Peak EnergyEnergy infrastructureAM6442https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672484/am3358-electrical-fuse-farm-fusefarmWed, 12 Aug 2026 00:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a82bec13-6ec7-43fe-a907-9ed1c8b9f551Koshi NinomiyaPart Number: AM3358 Dear Team, My customer has used the AM3358BZCZ100 in their system. And they are considering security measures. The AM3358BZCZ100 contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable, right? Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable – Production ID – Device Part Number (Unique JTAG ID) – Device Revision (Readable by Host ARM) Can the FuseFarm be used to write the following items? - JTAG restrictions - Key information - Security status Best Regards, Koshi NinomiyaAM3358https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1672481/am3358-high-secure-hs-deviceWed, 12 Aug 2026 00:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:001e8496-ccbd-4894-8848-6452661df369Koshi NinomiyaPart Number: AM3358 Dear Team, My customer has used the AM3358BZCZ100 in their system. And they are considering security measures. The AM3358 has a high-secure (HS) device. Is there a catalog part of the AM3358 which has HS? Or will the HS device of the AM3358 be custom part? Best Regards, Koshi NinomiyaAM3358https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1671266/mspm0g3507-pmbus-reading-failure/6447576Tue, 11 Aug 2026 23:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d338499d-d0c7-4b93-9fda-9823eb34c661Crane ShaoIt is the clock issue. Changing the clock from 40M to 32M addressed this issue.