TMS320F280049C: Hex record anomaly

Phil Gillaspy

Part Number: TMS320F280049C

Here is the beginning of my Intel format hex file:

:020000040008F2
:0200000049C1F4
:020000040009F1
:20000000064201443130187F4401A6421FA9A63B464A054446E4044446D486060A464501FE

So I expect to see in memory beginning at 0x80000: 49C1 FFFF FFFF FFFF

But after loading out file into memory, this is what I see in the memory browser:

0x00800000 0049 5AC1 FFFF FFFF

1) So the 49C1 is not in the first word, why not???

2) Well well, the memory browser shows the address 95AC1 which just happens to be the entry point for

00095ac1 00000008 f28004x_codestartbranch.obj (.text)

3) So the hex file has the 9 and C1 but just how did the 5A get there???

over 3 years ago

0 Phil Gillaspy over 3 years ago

Prodigy 210 points

I should have clarified that the code is being compiled and linked to run in flash Bank 1.

0 Vamsi Gudivada over 3 years ago in reply to Phil Gillaspy

TI__Guru* 87155 points

Hi Phil,

Let me review and get back to you in a day or two.

Thanks and regards,
Vamsi

0 Vamsi Gudivada over 3 years ago in reply to Vamsi Gudivada

TI__Guru* 87155 points

Hi Phil,

I am assigning this to our compiler team to help clarify this for you.

If needed, they will assign this back to the C2000 team.

Thanks and regards,
Vamsi

0 George Mock over 3 years ago

TI__Guru**** 251820 points

Please show the command you used to invoke the hex utility hex2000. If it refers to any command files, please show the contents of those files. Please copy and paste the text, and do not use a screen shot.

Thanks and regards,

-George

0 Phil Gillaspy over 3 years ago in reply to George Mock

Prodigy 210 points

Attached is the linker command file. As to the hex2000 command line, I have set the autogeneration of the hex file in the build settings and so I don't really know what the hex2000 command line looks like. I would suppose it is using the standard defaults.

#ifdef RUN_FROM_BANK0
/* Linker commands to generate execution out of Bank 0 */
MEMORY
{
PAGE 0 :

BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */

RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */

RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x001800

RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001F00

RESET : origin = 0x3FFFC0, length = 0x000002

/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002

// BANK 0 - on chip flash
FLASH_BANK0 : origin = 0x080002, length = 0x00EFF4

/* BANK 1 - on chip flash */
FLASH_BANK1 : origin = 0x090000, length = 0x00EFF8

/* Define end of RAMGSx memory used for RAM memory test */
RAM_TEST : origin = 0x013F00, length = 0x100

/* Define flash location to save CRC flash address */
/* when running out of Bank 0 */
CRC_BANK0 : origin = 0x8EFF6, length = 8

/* Define flash location to save CRC flash address */
/* when running out of Bank 1 */
CRC_BANK1 : origin = 0x9EFF8, length = 8

} // end MEMORY

SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : >>FLASH_BANK0 PAGE = 0, ALIGN(4)
.cinit : > FLASH_BANK0, PAGE = 0, ALIGN(4)
.pinit : > FLASH_BANK0, PAGE = 0, ALIGN(4)
.switch : > FLASH_BANK0, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM0 | RAMM1, PAGE = 0

.data : > RAMLS5, PAGE = 0
.sysmem : > RAMLS5, PAGE = 0

/* Initalized sections go in Flash */
.econst : > FLASH_BANK0, PAGE = 0, ALIGN(4)
.ebss : > RAMLS4 | RAMLS5, PAGE = 0
.esysmem : > RAMLS5, PAGE = 0
.cio : > RAMM1, PAGE = 0

/* Allocate IQ math areas: */
IQmath : > RAMGS1, PAGE = 0 /* Math Code */
IQmathTables : > RAMGS1, PAGE = 0
.TI.ramfunc : {} LOAD = FLASH_BANK0,
RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)

rts_lib
{
--library=rts2800_fpu32.lib(.text)
} > FLASH_BANK0

UNION run = FLASH_BANK0, PAGE = 0
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}

/* Define section used for RAM memory test */
ramTestSection : > RAM_TEST, PAGE = 0

/* Define section for storage location of CRC's address */
crcBank0AddressSection : > CRC_BANK0, PAGE = 0, ALIGN(4)
crcBank1AddressSection : > CRC_BANK1, PAGE = 0, ALIGN(4)

} // end SECTIONS
#endif // RUN_FROM_BANK0

#ifdef RUN_FROM_BANK1
/* Linker commands to generate execution out of Bank 1 */
MEMORY
{
PAGE 0 :

BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */

RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */

RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001F00

RESET : origin = 0x3FFFC0, length = 0x000002

/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002

// BANK 0 - on chip flash
FLASH_BANK0 : origin = 0x080002, length = 0x00EFF4

/* BANK 1 - on chip flash */
FLASH_BANK1 : origin = 0x090000, length = 0x00EFF8

/* Define end of RAMGSx memory used for RAM memory test */
RAM_TEST : origin = 0x013F00, length = 0x100

/* Define flash location to save CRC flash address */
/* when running out of Bank 0 */
CRC_BANK0 : origin = 0x8EFF6, length = 8

/* Define flash location to save CRC flash address */
/* when running out of Bank 1 */
CRC_BANK1 : origin = 0x9EFF8, length = 8

} // end MEMORY

SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : >>FLASH_BANK1 PAGE = 0, ALIGN(4)
.cinit : > FLASH_BANK1, PAGE = 0, ALIGN(4)
.pinit : > FLASH_BANK1, PAGE = 0, ALIGN(4)
.switch : > FLASH_BANK1, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM0 | RAMM1, PAGE = 0

.data : > RAMLS5, PAGE = 0
.sysmem : > RAMLS5, PAGE = 0

/* Initalized sections go in Flash */
.econst : > FLASH_BANK1, PAGE = 0, ALIGN(4)
.ebss : > RAMLS4 | RAMLS5, PAGE = 0
.esysmem : > RAMLS5, PAGE = 0
.cio : > RAMM1, PAGE = 0

/* Allocate IQ math areas: */
IQmath : > RAMGS1, PAGE = 0 /* Math Code */
IQmathTables : > RAMGS1, PAGE = 0
.TI.ramfunc : {} LOAD = FLASH_BANK1,
RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)

rts_lib
{
--library=rts2800_fpu32.lib(.text)
} > FLASH_BANK1

UNION run = FLASH_BANK1, PAGE = 0
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}

/* Define section used for RAM memory test */
ramTestSection : > RAM_TEST, PAGE = 0

/* Define section for storage location of CRC's address */
crcBank0AddressSection : > CRC_BANK0, PAGE = 0, ALIGN(4)
crcBank1AddressSection : > CRC_BANK1, PAGE = 0, ALIGN(4)

} // end SECTIONS
#endif // RUN_FROM_BANK1

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Phil Gillaspy over 3 years ago in reply to Phil Gillaspy

Prodigy 210 points

Looking through the settings for the hex2000 output utility, there are no options set. Only the output format is set to -intel.

0 George Mock over 3 years ago in reply to Phil Gillaspy

TI__Guru**** 251820 points

Phil Gillaspy said:
Attached is the linker command file.

Unfortunately, that doesn't help.

Phil Gillaspy said:
I have set the autogeneration of the hex file in the build settings

I presume this means you build with CCS. Perform a build that includes invoking the hex utility hex2000. All of the commands, and their output, appears in the Console (not Problems) view. Find the invocation of the hex utility hex2000, and all the system response related to it. Please copy and paste all of that text into your next post.

Thanks and regards,

-George

0 Phil Gillaspy over 3 years ago in reply to George Mock

Prodigy 210 points

Okay here is the hex2000 command line:

"C:/ti/ccs1100/ccs/tools/compiler/ti-cgt-c2000_21.6.0.LTS/bin/hex2000" --diag_wrap=off --intel -o "MCEDuplex.hex" "MCEDuplex.out"

+1 George Mock over 3 years ago in reply to Phil Gillaspy

TI__Guru**** 251820 points

You have the same problem described in this forum thread. Use the same solution: add --romwidth=16.

Phil Gillaspy said:
So the hex file has the 9 and C1 but just how did the 5A get there???

When you run this command ...

Phil Gillaspy said:
hex2000" --diag_wrap=off --intel -o "MCEDuplex.hex" "MCEDuplex.out"

You get a diagnostic similar to ...

warning: Data is being written to auto-generated file MCEDuplex.i01

When you use --intel, the default --romwidth=8. This means two different output files are created: MCEDuplex.hex and MCEDuplex.i01. The even numbered bytes are in one file, and the odd number bytes are in the other. So, the 5A comes from MCEDuplex.i01.

By the way, the same solution also resolves your other thread. More details in that thread.

Thanks and regards,

-George

0 Phil Gillaspy over 3 years ago in reply to George Mock

Prodigy 210 points

Thank you very much. All is well now.

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TMS320F280049C: Hex record anomaly