Other Parts Discussed in Thread: TMDSCNCD28379D, C2000WARE
Hello,
First, this is not for the indicated TI part number, but I did not know where else to ask this subject question since I can't seem to get an answer elsewhere.
I am in the process of wrapping up a board layout with standard peripheral bus (EMIF) composed of the standard address, data and control signal (WE,OE). I have a board stack up such that the reference plane is 0.1mm below the traces. The rise time from the processor is a 1.5ns minimum. When reviewing the cross talk calculations from various websites I end up with an insane value for any track above 10mm. The values are well over the V low for the chip set of 0.15*Vdd ~0.495V with a track separation of 1H (0.1mm) and maximum trace length for the bus of around 70mm. The only way I can get a reasonable number is to use a separation of 4H. In the past, I have always routed my address/data bus with separation of twice the trace width and never had any issues. I started watching several videos from Eric Bogatin, Rick Hartly and Robert Feranec on YouTube about victim traces and aggressor traces. This got me to rethinking my address and data busses. However, when looking at layout strategies, the track separations become unrealistic for anything I have seen or done. So, this got me to thinking. Is cross-talk only an edge event, I.E. only occurs at the rise and fall edges as the signal propagates down the track? I did a lot of searching and there seems to be no discussion on this. Therefore, I will pose this question here.
Is cross-talk only an edge event or is it a steady state coupling problem? The reason I ask is that traditional data busses will send their address and data signals first, and then some time later raise the control signal line, either WE or OE. Then at some time later, read the data at the receiver. If cross-talk is an edge event and not steady state, then this would make sense with the track spacing that I have used and what I have seen on other systems. If cross-talk is steady state, then it seems to me that the bus would never work with the traditional track separations I have used or seen.
Does anyone have further insight into this. I would really like to stay with my twice track width separation or actually just 2H if H >= 0.1mm for a given stack up for all of my parallel interface busses that I use on microcontroller designs.
Another thing that crossed my mind is what would happen if I created a split between adjacent tracks on the reference plane. In principal, this could break the coupling fields since there would be no reference between the tracks area on the reference plane.
