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F28M35M52C: Decoupling +1.8V Internal VREG Output of Concerto F28M35x Device

Part Number: F28M35M52C
Other Parts Discussed in Thread: CONTROLSUITE


I have some confusion about the value of the decoupling capacitors used for +1.8V internal regulator output pins. The section 8.9.1 "Analog Subsystem: Internal 1.8-V VREG", device datasheet SPRS742L, p.173, stipulates that "... a 1.2-μF (10% tolerance) capacitor is required for each VDD18 pin to stabilize the internally generated voltages". End of citation. On the other side, the schematic diagram for Concerto DIMM100 Control Card in controlSUITE, file 514982E_CONCERTO_DIMM100_RELEASE2_00_ALLEGRO_DEC_17_2011.pdf, shows these capacitors be of 2.2uF value each.

Q1. What document is correct - the datasheet or the schematic diagram? Is 1.2uF value mentioned in the datasheet the only value acceptable for the purpose and must be strictly followed or is it simply the minimum acceptable value to stabilize the internal +1.8V VREG regulator? If 1.2uF is the minimum value, what is the acceptable min-to-max selection range?

Q2. Are there any ESR requirements for these capacitors?

Please clarify this situation for me.

Thank you for your support.

Regards, Michael

  • Michael,

    Your assumption in Q1 is correct.  The 1.2uF is a min value, I think the 2.2uF was used for BOM management reasons on that particular design and it will also work.  The only drawback of a larger cap(>2.2uF) is that the initial power up will take longer as the cap has to charge from a power off state.

    I'm not aware of any strict ESR requirements on these caps, the voltage regulator is LDO style so there shouldn't be any frequencies involved(like with a switching regulator) that would cause any ESR issues.



  • Thank you, Matthew!
    Looks like it answers my question.