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TMS320F28031: Possible problem if Shadow Load and EPWM1.interrupt occur at Counter = Zero

Part Number: TMS320F28031

Hi Experts,
I have an ADC ISR that runs at 40kHz.
At the end of it, I enable an EPWM1.interrupt, wherein I calculate values for EPWM1 and EPWM2 parameters.
EPWM2 is phased to EPWM1 at COUNTER = CMPB, both EPWMs use COUNT UP, Dead Band modules are used. is triggered by event COUNTER = ZERO, and both EPWMs have SHADOW LOAD set to COUNTER = ZERO.
The chip controls LLC power module that operates with a switching frequency (Fsw) range of (56kHz-170kHz).
The ADC ISR is not sync'd with the Fsw.

For corner cases and especially for instances when the Fsw is at multiples of the ADC ISR frequency (80kHz, 120kHz, 160kHz),
will there be a problem when the ADC ISR ends at exactly COUNTER = ZERO or at least near COUNTER = ZERO?
Which one has a higher priority, SHADOW LOAD or servicing internal interrupt triggers?
My worry is that the SHADOW LOAD may not be finished transferring contents of shadow registers to active registers and the gets serviced.
If that happens, not all EPWM parameters may be captured at the same time, and will screw up the PWM signals.


  • Dom,

    I believe knowing the priority of this doesn't help us. Lets assume the worst case, the shadow load did occur after the ISR trigger: In this case the processor still has to preform a context store after the ISR trigger. This store will take about 12 cycles, the shadow load should happen in only one clock edge so it should be complete well before any ISR code is executed. 

    I might help to know that the core doesn't need to move these values, it happens automatically through embedded logic in the PWM module.


  • Hi Cody,
    Thanks for the response and it's the information I need.

    Is there a document that indicates this 12 cycles? Or I might have missed it somewhere.
    I have found a few sources (listed below), but none of them directly refer to F28031 device.
    Or are these information same for the C28x devices?
    So the internal interrupt latency range (which includes the context save) would be 8-14 cycles, is my understanding correct?

    F2803x TRM Section Interrupt Operation Sequence indicates SPRU430 as reference.
    SPRU430 indicates in Example 3-1, Full Context Save/Restore = 8-16 cycles
    F28004x_Microcontroller_1-0.pdf (TMS320F28004x Microcontroller Workshop) indicates Interrupt Latency for internal interrupts = 14 cycles minimum
    CLA Hands On Workshop - Part 1 Introduction (tutorial video), gives an example of Context Save with 8-14 cycles.


  • Dom, I didn't look up the number, I just went with the number in my head... so emphasis on "About" 12 cycles. 

    You are in the correct range, but there are a number of factors which could contribute to the number of cycles required, please see this page for a more detailed description.