I have an ADC ISR that runs at 40kHz.
At the end of it, I enable an EPWM1.interrupt, wherein I calculate values for EPWM1 and EPWM2 parameters.
EPWM2 is phased to EPWM1 at COUNTER = CMPB, both EPWMs use COUNT UP, Dead Band modules are used.
EPWM1.int is triggered by event COUNTER = ZERO, and both EPWMs have SHADOW LOAD set to COUNTER = ZERO.
The chip controls LLC power module that operates with a switching frequency (Fsw) range of (56kHz-170kHz).
The ADC ISR is not sync'd with the Fsw.
For corner cases and especially for instances when the Fsw is at multiples of the ADC ISR frequency (80kHz, 120kHz, 160kHz),
will there be a problem when the ADC ISR ends at exactly COUNTER = ZERO or at least near COUNTER = ZERO?
Which one has a higher priority, SHADOW LOAD or servicing internal interrupt triggers?
My worry is that the SHADOW LOAD may not be finished transferring contents of shadow registers to active registers and the EPWM1.int gets serviced.
If that happens, not all EPWM parameters may be captured at the same time, and will screw up the PWM signals.