Dear team:
Is there any difference and connection between XINTF synchronous sampling and asynchronous sampling?
What is the impact on using XINTF communication with FPGA?
Best regards
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Dear team:
Is there any difference and connection between XINTF synchronous sampling and asynchronous sampling?
What is the impact on using XINTF communication with FPGA?
Best regards
Green,
My interpretation is that the only difference between the two sampling modes for XREADY is that the asynchronous mode requires the signal to be asserted 3*XTIMCLK cycles before the end of LEAD+ACTIVE, whereas the synchronous mode only requires the signal to be asserted 1*XTIMCLK cycle before the end of LEAD+ACTIVE.
Thus, the synchronous mode has a slightly larger window in which XREADY can be asserted for a given LEAD+ACTIVE configuration. There is also the add-on effect that the asynchronous mode requires a longer minimum LEAD+ACTIVE configuration to accommodate the additional 2*XTIMCLK cycles.
The impact to FPGA would depend on its specific implementation.
-Tommy