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TMS320F280023: Flash Memory Map - Byte Access

Part Number: TMS320F280023

Hello support team,

F28002x has 16bit Word memory map, e.g. Sector 0, 4K x 16, 0x0008 0000 to 0x0008 0FFF. When I go to a addess, I get a 16bit Word.

- Can I also acces a byte using address? Does high byte at addess 0x80000 have its eigen address?

- When I generate a Intel HEX file with "--memwidth=8 --diag_wrap=off --intel", the adress is doubled. the first adress is 0x100000 instead of 0x80000. With "--memwidth=16 --diag_wrap=off --intel" I have correct address but 2 files *.hex and *.i01 for high byte. Can I flash the HEX file like this topic in both cases (memwidth=8 and memwidth=16)?

e2e.ti.com/.../3637751

In case of memwidth=16, should I flash 2 files or the SW can automatically join both *.hex and *.i01 files?

Regards,

Nguyen

  • Hi Nguyen,

    You can not access a byte.  If you need to access a byte, you may read 16-bits and discard the byte that you don't need.  

    I remember romwidth and memwidth should be 16 for C28x.  

    Also, C2000 Hex utility generates separate hex files for page 0 and page 1. You will notice a warning from the hex utility about this when you compile. If you load only one hex file, you will miss the other page's contents.  To avoid this issue, in general, when you use hex files, map all the initialized sections to page 0 in the linker cmd file.

    Thanks and regards,
    Vamsi

  • Hi Vamsi,

    Thank you for the reply. Could you please tell me how to do this? 

    To avoid this issue, in general, when you use hex files, map all the initialized sections to page 0 in the linker cmd file.

    Do we have a manual or example project for this?

    And after that I have to load both files or how should I do?

    Regards,

    Quy

  • Nguyen,

    Could you check if your linker cmd file and see if anything is mapped to page 0 and page 1 separately?  

    If there are no pages defined, then this should not be an issue.  If pages are defined in the linker cmd file, I can help you modify it to move everything to page 0 - Once this is done, there should be only one file for load.

    Thanks and regards,
    Vamsi 

  • Hello Vamsi,

    I don't get correctly what "page" means. Does it means the "bank" (page 0 <=> BANK0) or does it means "sector" (page 0 <=> Sector0) 

    My derivate has only one bank 0 and 8 sectors

    the linker file is as following

    MEMORY
    {
       BEGIN            : origin = 0x080000, length = 0x00003B
       BOOT_RSVD    : origin = 0x00000002, length = 0x00000126
       RAMM0            : origin = 0x00000128, length = 0x000002D8
       RAMM1            : origin = 0x00000400, length = 0x000003F8     /* on-chip RAM block M1 */
    // RAMM1_RSVD       : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    /* RAMLS4           : origin = 0x0000A000, length = 0x00000800
       RAMLS5           : origin = 0x0000A800, length = 0x00000800
       RAMLS6           : origin = 0x0000B000, length = 0x00000800
       RAMLS7           : origin = 0x0000B800, length = 0x00000800*/
       
       /* Combining all the LS RAMs */
       RAMLS4567        : origin = 0x0000A000, length = 0x00002000
       RAMGS0           : origin = 0x0000C000, length = 0x000007F8
    // RAMGS0_RSVD      : origin = 0x0000C7F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    
    //  FLASHBANK1       : origin = 0x00080000, length = 0x0000FFF0
    //  FLASH_BANK1_RSVD : origin = 0x0008FFF0, length = 0x00000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
       BOOTROM          : origin = 0x003F0000, length = 0x00008000
       BOOTROM_EXT      : origin = 0x003F8000, length = 0x00007FC0
       RESET            : origin = 0x003FFFC0, length = 0x00000002
       /* Flash sectors */
       /* BANK 0 */
       FLASH_BANK0_SEC0  : origin = 0x08003B, length = 0x000FC5 /* on-chip Flash */
       FLASH_BANK0_SEC1  : origin = 0x081017, length = 0x000FE9 /* on-chip Flash */
       FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
       FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x000FF0 /* on-chip Flash */
    // FLASH_BANK0_SEC15_RSVD     : origin = 0x08FFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    }
    
    
    SECTIONS
    {
       codestart        : > BEGIN, ALIGN(8)
       .text            : >> FLASH_BANK0_SEC0 | FLASH_BANK0_SEC1,   ALIGN(8)
       .cinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
       .switch          : > FLASH_BANK0_SEC1,  ALIGN(8)
       .reset           : > RESET,                  TYPE = DSECT /* not used, */
    
       .stack           : > RAMM1
    
       .init_array      : > FLASH_BANK0_SEC1,  ALIGN(8)
       .bss             : > RAMLS4567
       .bss:output      : > RAMLS4567
       .bss:cio         : > RAMLS4567
       .const           : > FLASH_BANK0_SEC1,  ALIGN(8)
       .data            : > RAMLS4567
       .sysmem          : > RAMLS4567
    
        ramgs0 : > RAMGS0
    
      GROUP
       {
           .TI.ramfunc
           {
              -l FlashAPI_F28002x_FPU32.lib
           }
       }  LOAD = FLASH_BANK0_SEC1,
        RUN = RAMLS4567,
        LOAD_START(RamfuncsLoadStart),
        LOAD_SIZE(RamfuncsLoadSize),
        LOAD_END(RamfuncsLoadEnd),
        RUN_START(RamfuncsRunStart),
        RUN_SIZE(RamfuncsRunSize),
        RUN_END(RamfuncsRunEnd),
        ALIGN(8)
    }

    Regards,

    Quy

  • Quy,

    Looks like you are using the latest linker cmd files - No pages in them - that's good.  You don't need to worry about pages.

    Just use romwidth and memwidth as 16 for intel hex format - you should get single file.

    Let me know if it does not.  

    Thanks and regards,
    Vamsi