Hello Champs,
We can only find USB and EtherCAT registers base address for C28 in F2838x TRM but cannot find USB and EtherCAT registers base address for CM.
Would you please help? Thanks!
Best Regards,
Linda
Hello Siddharth, Hello Vivek,
For EtherCAT on CM, the offset address for ESC registers are listed as below in C2000ware EtherCAT demo codes:
#define ESCSS_O_IPREVNUM 0x0U // IP Revision Number
#define ESCSS_O_INTR_RIS 0x4U // EtherCATSS Interrupt Raw Status
#define ESCSS_O_INTR_MASK 0x8U // EtherCATSS Interrupt Mask
#define ESCSS_O_INTR_MIS 0xCU // EtherCATSS Masked Interrupt Status
#define ESCSS_O_INTR_CLR 0x10U // EtherCATSS Interrupt Clear
#define ESCSS_O_INTR_SET 0x14U // EtherCATSS Interrupt Set to emulate
#define ESCSS_O_LATCH_SEL 0x18U // Select for Latch0/1 inputs and LATCHIN input
#define ESCSS_O_ACCESS_CTRL 0x1CU // PDI interface access control config.
#define ESCSS_O_GPIN_DAT 0 x20U // GPIN data capture for debug & override
#define ESCSS_O_GPIN_PIPE 0x24U // GPIN pipeline select
#define ESCSS_O_GPIN_GRP_CAP_SEL 0x28U // GPIN pipe group capture trigger
#define ESCSS_O_GPOUT_DAT 0x2CU // GPOUT data capture for debug & override
#define ESCSS_O_GPOUT_PIPE 0x30U // GPOUT pipeline select
#define ESCSS_O_GPOUT_GRP_CAP_SEL 0x34U // GPOUT pipe group capture trigger
#define ESCSS_O_MEM_TEST 0x38U // Memory Test Control
#define ESCSS_O_RESET_DEST_CONFIG 0x3CU // ResetOut impact or destination config
#define ESCSS_O_SYNC0_CONFIG 0x40U // SYNC0 Configuration for various triggers
#define ESCSS_O_SYNC1_CONFIG 0x44U // SYNC1 Configuration for various triggers
It's different from that on C28 described as Table31-18 in F2838x TRM:
Would you please also update the offset address table for ESCSS registers on CM? Thanks!
Best Regards,
Linda
