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TMS320F28386D: DCC configuration

Part Number: TMS320F28386D
Other Parts Discussed in Thread: C2000WARE

Hello,

I am having a hard time ensuring I am going to put the correct values inside the different counter/seed registers.

So I'll expose to you my use cases so that you can help me figuring it out.

First use case

I want to monitor the external 20MHz 50ppm crystal connected on X1 (clock source 0) using INTOSC1 (clock source 1).

Second use case

I want to monitor the external 20MHz 50ppm crystal connected on X1 (clock source 0) using INTOSC1 (clock source 1).

Third use case

I want to monitor an external 1MHz 50ppm crystal connected on a GPIO and redirected on the Input X-BAR input 15 (clock source 1 of the DCC) using INTOSC1 (clock source 0).

Fourth use case

I want to monitor an external 1MHz 50ppm crystal connected on a GPIO and redirected on the Input X-BAR input 16 (clock source 0 of the DCC) using INTOSC0 (clock source 1).

For all four cases, my end goal is to perform a 1% tolerance monitoring of the crystals frequencies (more than the 50ppm but we don't need a very close monitoring).

Can you please help me out and in particular guide me for each case on the computation of the different steps:

  • DCC error
  • Window
  • Frequency error allowed
  • Total error
  • Counter0
  • Valid0
  • Counter1

Thank you,

Best regards

Clément

  • Hi Clement,

    You can refer to the device TRM for the DCC value calculations. You can also use the C2000ware driverlib which provides APIs that calculates these values configures the DCC registers. DCC_verifyClockFrequency function for one-shot verification and DCC_continuousMonitor for continuous monitoring.

    Regards,

    Veena

  • I obviously already refered to the TRM before writing and the tolerance part is where I am not sure (both the tolerance of the INTOSC1/INTOSC2 and our crystal one), the TRM isn't clear enough about that.

    I don't see the two functions you are refering to in the dcc.h/dcc.c files of C2000Ware_3_02_00_00.

    But using those functions is anyways not an answer as I need to justify the computation (we are developing for the aeronautical domain so we don't use your code base).

    Best regards,

    Clément

  • Hi Clément,

    The functions are present C2000ware v3.04.00.

    In the TRM steps, the Tolerance is desired tolerance for DCC error. Lower the tolerance, longer the window.

    Along with the DCC error, there is a possibility of error due to frequency variance of the clock used for DCC comparison. In case of using INTOSC1/2, the frequency variance is +/-3%

    From device datasheet:

    I believe other steps are clear.

    Regards,

    Veena

  • Just to be sure when configuring the DCC, the clock source 0 is the element to be monitored or is it the clock source 1 one or can it be both ?

    Where would I put into the equation the error on the clock source 0 and the one on the clock source 1 exactly ?

    Regards,

    Clément

  • Hi Clément,

    Basically, DCC monitors the ratio of the frequencies of clock1 and clock2, whether it maintains a constant value (within allowed tolerance). 

    Lets say you want to monitor/measure XTAL frequency using INTOSC1 as  reference, you can configure clock0 as XTAL and clock1 as INTOSC1. Since these are different clock sources, you need to take into consideration, the freq variance of INTOSC1. The steps documented in the TRM mentions adding the frequency variance of the clock which acts as the reference clock. I will check with the module experts whether we need take in freq variance of both the clocks.

    Lets say you want to monitor PLL output. PLL is using XTAL as the source and you want to make sure PLL/XTAL maintains a constant frequency ratio. In this case, since both are from the same clock source, you need not add the freq variance error in the DCC calculations.

    Regards,

    Veena

  • Hi Veena,

    Lets say you want to monitor/measure XTAL frequency using INTOSC1 as  reference, you can configure clock0 as XTAL and clock1 as INTOSC1. Since these are different clock sources, you need to take into consideration, the freq variance of INTOSC1. The steps documented in the TRM mentions adding the frequency variance of the clock which acts as the reference clock. I will check with the module experts whether we need take in freq variance of both the clocks.

    Thanks.

    My understanding is that variance of clock source 0 is to be put n the "Window" formula and variance of clock source 1 should be in "Frequency error allowed" formula. But I might be wrong ?

    Lets say you want to monitor PLL output. PLL is using XTAL as the source and you want to make sure PLL/XTAL maintains a constant frequency ratio. In this case, since both are from the same clock source, you need not add the freq variance error in the DCC calculations.

    Yes but in that case, you would integrate that as the tolerance in the "Window" formula no ? Or is the tolerance in that formula rather the expectations in terms of monitoring tightness ?

    Regards,

    Clément

  • Hi Clement,

    Tolerance defined in the Window calculation is DCC induced, this tolerance does not account for inaccuracy in Clk0 or Clk1 frequency. Meaning for DCC Error you define tolerance of this error in percentage, if you want this error to be lower tolerance and average out over time you increase the window of measurement, that means your desired tolerance of DCC error is less, but if you have higher tolerance of this error where you are only doing gross check, your window of measurement can be smaller.

    Allowable Frequency Error

    It accounts for error in clk0 and/or clk1, this will define your VALID window. Meaning for example if Clk0 (XTAL) is expected to have frequency variance of 1% and Clk1 (INTOSC2) is expected to have frequency variance of 3%, then they both needs to be added to account for total allowable frequency tolerance of 4% (considering worst case scenario). In this scenario since both the clocks are asynchronous in nature the allowable error/variance needs to be added.

    In another scenario lets say if your Clk0 is INTOSC2 with 3% tolerance, and Clk1 is PLL (using INTOSC2 as a clock source) with allowable tolerance of 0.1%, then both the clocks are synchronous in nature any error in ITNOSC2 will also show up on PLL, so in this case only allowable frequency error on PLL that is 0.1% needs to be accounted because 3% variance on INTOSC2 gets cancelled out.

    Hopefully this clears the doubt. Let me know if you have any more questions.

    Best Regards,

    Nirav

  • Yes it cleared all remaining doubts thanks !

    I must admit your answer is pretty clear, in particular the end examples, you should consider adding these to the TRM it could help others.

    Best regards,

    Clément