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TMS320F28374D: Bulk data exchange using GSRAMs

Part Number: TMS320F28374D

Hello,

I am trying to exchange a bulk of data between CPU1 and CPU2 of the TMS320F28374D, more than the MSG RAMs can handle. For testing
I created two arrays, one on each CPU.

What I originally wanted to archieve is, that both CPUs have one array where one CPU can store data into and the other CPU can only read
the same data from the array, which he can access because it is named the same like on the other CPU and has equal start adress and length.

What I did was:

Using GSRAM8 and GSRAM9 for the transfer. GSRAM8 is R/W for CPU1 and R for CPU2, GSRAM9 vise versa.
I created and assigned data sections in the memory maps of both CPUs:

SECTIONS
{
...

CPU1_TO_CPU2_GS : > RAMGS8 PAGE = 1
CPU2_TO_CPU1_GS : > RAMGS9 PAGE = 1

...
}

Then I created both arrays and used pragma to assign them to the correct memory areas. I did this in both codes of the CPUs with
the same names, so both look exactly like this:

Uint32 CPU1_TO_CPU2_Array[256] = 0;
Uint32 CPU2_TO_CPU1_Array[256] = 0;

#pragma DATA_SECTION(CPU1_TO_CPU2_Array,"CPU1_TO_CPU2_GS");
#pragma DATA_SECTION(CPU2_TO_CPU1_Array,"CPU2_TO_CPU1_GS");


Furthermore I assigned the master role for GSRAM8 to CPU1 and for GSRAM9 to CPU2. Also I waited until the ownership
is assigned corretly; both happens in the code of CPU1:

EALLOW;
MemCfgRegs.GSxMSEL.bit.MSEL_GS8 = 0; // CPU1 can Read/Write; CPU2 only Read
MemCfgRegs.GSxMSEL.bit.MSEL_GS9 = 1; // CPU2 can Read/Write; CPU1 only Read
EDIS;
while(!(MemCfgRegs.GSxMSEL.bit.MSEL_GS9 == 1 && MemCfgRegs.GSxMSEL.bit.MSEL_GS8 == 0));


When I use debug now, it works but only as long as I am using only these two arrays for test purpose. When I create more arrays this way, they will
be mapped to different memory spaces in the specified area on both CPUs. Then there is no match between the same arrays on CPU1 and CPU2,
so it doesn't work anymore.

Is there a way to create arrays on both CPUs with the same memory start adress, without assigning them manually to that adress? Or is there another
way to achieve a bulk exchange of data between both CPUs?

Thank you in advance!

  • Viktor,

    Your implementation with the #pragma and Data_Section is the only way I know of to force the linker to allocate areas to specific addresses.  So if you wanted to have multiple blocks with fixed addresses you would need to declare multiple of these as you mention.

    I was thinking you could use the DMA(s) to transfer the data, the DMA has access to all Gx RAMs.  This would save you the CPU overhead and would also arbitrate automatically if there were collisions. 

    Adding on that you could use the IPC to send the address start/length of the data array across to the other CPU.  This would prevent you from having to hard allocate things in the linker as above.  You could then use the IPC Interrupt to kick off a one shot DMA event to read the data.

    Let me know if this helps, or we can brainstorm some more.

    Best,

    Matthew

  • Hey Matthew,

    thank you very much for your detailed answer!

    Then I'll allocate the data manually and I will use the DMA to reduce my overhead in communications. 

    Best regards,

    Viktor