TMS320F28335: Using Code Security Module(CSM) makes ISR execution time being longer

Yi-Lin

Part Number: TMS320F28335
Other Parts Discussed in Thread: CONTROLSUITE

We are developing motor drive application with EtherCAT on TMS320F28335. It has a PWM ISR that runs every 125us.

The execution time of that ISR is around 88ms before applying Code Security Password to the project. However, if we use On-Chip Programmer provided by CCS to lock the DSP, the execution time comes to almost 125us.

We found the [FAQ] Common CSM and Flash Questions post had mentioned the code run in unsecure memory can't read/write to memory that is secure.

Would this be the reason that the PWM ISR is longer than expectation after using CSM?(e.g. the function being called in ISR is located in unsecure memory and accessing data in secure area)

Please help

Thanks and regards,

Yi-Lin

over 4 years ago

0 Hareesh Janakiraman over 4 years ago

TI__Guru* 95315 points

Yi-Lin said:
The execution time of that ISR is around 88ms before applying Code Security Password to the project. However, if we use On-Chip Programmer provided by CCS to lock the DSP, the execution time comes to almost 125us.

You probably meant 88 us, not 88 ms.

I presume the 88 us number pertains to code running in flash. Please confirm all numbers you have quoted in your post pertains to code running in flash.

Yi-Lin said:
Would this be the reason that the PWM ISR is longer than expectation after using CSM?

Any read access to secure areas will be simply blocked and your application will not work as expected. Is that the case? In other words, your application won't take longer to run. It simply won't work properly.

0 Yi-Lin over 4 years ago in reply to Hareesh Janakiraman

Intellectual 545 points

Dear Hareesh,

Appreciate for your reply.

Sorry for the wrong unit causing confuse and pleas let us correct the numbers because we accidently recorded wrong signal yesterday...

The PWM ISR is being triggered every 125us, the execution time is 28 us before we use CSM. The PWM ISR is being running in SARAM L0~L4, but some functions located in Flash will be called by PWM ISR during the operation. We used gpio signal for monitoring the status of PWM ISR.

Here are two experiment result we get today:

1. Under 2ms DC Cycle time of EtherCAT operation, the PWM ISR execution time with CSM become 69 us

2. Under 250us DC Cycle of EtherCAT operation, the system crashed at the end and the PWM ISR execution time become forever.

We also notice that with CSM function, the execution time of other ISR code that running in flash extended from 33 us to 100 us.

The waveform of the ISR status without CSM under 250us DC Cycle of EtherCAT operation:

C1: DC ISR(for EtherCAT); C2: PWM ISR; C3: SM2 ISR(for EtherCAT)

The waveform of the ISR status with CSM under 250us DC Cycle of EtherCAT operation:

C1: DC ISR(for EtherCAT); C2: PWM ISR; C3: SM2 ISR(for EtherCAT)

Here is the memory configuration of our project. The PWM ISR is allocated to ramfuncs, and all the data is being stored in unsecured area.

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

	ZONE0		: origin = 0x004000, length = 0x001000		/* XINTF zone 0 */

	RAML0to4	: origin = 0x008000, length = 0x005000		/* on-chip RAM block L0~L5 */

	ZONE6		: origin = 0x100000, length = 0x100000		/* XINTF zone 6 */ 
	ZONE7A		: origin = 0x200000, length = 0x00FC00		/* XINTF zone 7 - program space */ 

	FLASH_E		: origin = 0x318000, length = 0x008000     /* FLASH_E: For system program storing in FLASH */
	FLASH_D		: origin = 0x320000, length = 0x008000     /* FLASH_D: For functions operating in flash */
	FLASH_C		: origin = 0x328000, length = 0x008000     /* FLASH_C: For functions operating in flash */
	FLASH_B		: origin = 0x330000, length = 0x008000     /* FLASH_B: For functions operating in ram (ramfuncs)*/
	FLASH_A		: origin = 0x338000, length = 0x007F80     /* FLASH A: Remain blank preventing from dead-lock @ 0x33FF80 ~ 0x33FFFF */


	CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
	BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
	CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
	OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
	ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */

	IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
	IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
	FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
	ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
	RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
	VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1     
	BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
	RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
	RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

	RAML5to6    : origin = 0x00D000, length = 0x002000     /* on-chip RAM block L6 */
	RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L7 */
	FPGA_RAM1_1	: origin = 0x204000, length = 0x000800     /* FPGA RAM 1.1, Store SDO object values */
	FPGA_RAM1_2	: origin = 0x204800, length = 0x000800     /* FPGA RAM 1.2, Store SDO object ECC values */
	FPGA_RAM2	: origin = 0x205000, length = 0x001000     /* FPGA RAM 2, Store CiA402 object values */
	FPGA_RAM3to4: origin = 0x206000, length = 0x002000     /* FPGA RAM 3&4, Store oscilloscope data */
	ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */

	FLASH_H		: origin = 0x300000, length = 0x008000     /* FLASH_H: For system data storing in FLASH */
	FLASH_G		: origin = 0x308000, length = 0x008000     /* FLASH_G: For the FLASH Default Specific Object values */
	FLASH_F		: origin = 0x310000, length = 0x008000     /* FLASH_F: For the FLASH Default CiA402 Object values */
	
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */

	.cinit              : > FLASH_E,		PAGE = 0
	.pinit              : > FLASH_E,		PAGE = 0
	.text               : > FLASH_C,		PAGE = 0
	.switch             : > FLASH_E,		PAGE = 0

	codestart           : > BEGIN,			PAGE = 0

	ramfuncs            : LOAD = FLASH_B//FLASHD, 
                         RUN = RAML0to4, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

	rts2800_lib_Flash	: > FLASH_E,		PAGE = 0
	{
		rts2800_fpu32.lib <*> (.text)
	}

	Flash28_API			:
	{
		-l Flash28335_API_V210.lib(.econst)
		-l Flash28335_API_V210.lib(.text)
	}
						 LOAD = FLASH_B,
						 RUN = RAML0to4,
                         LOAD_START(_Flash28_API_LoadStart),
                         LOAD_END(_Flash28_API_LoadEnd),
                         RUN_START(_Flash28_API_RunStart),
                         PAGE = 0

	Auto_Tuning_Code	: > FLASH_D,		PAGE = 0

	Spec_Object			: > FPGA_RAM1_1,	PAGE = 1
	Spec_Object_ECC		: > FPGA_RAM1_2,	PAGE = 1
	CiA402Bkup_Object	: > FPGA_RAM2,		PAGE = 1
	Oci_Scop_Buff_SEC	: > FPGA_RAM3to4,	PAGE = 1

	DEF_SPEC_OBJ		: > FLASH_G,		PAGE = 1
	DEF_CIA402_OBJ		: > FLASH_F,		PAGE = 1
	/* Allocate uninitalized data sections: */
	.stack              : > RAMM1,			PAGE = 1
	.ebss               : > RAML5to6,		PAGE = 1
	.econst             : > FLASH_H,		PAGE = 1
	//.esysmem            : > HRAML0,		PAGE = 1//using this memory region will cause ILLEGAL_ISR() in APPL_GenerateMapping()
	.esysmem			: > RAMM1|RAML7,	PAGE = 1
	.sysmem				: > RAMM1|RAML7,	PAGE = 1
	/* Initalized sections go in Flash */
	/* For SDFlash to program these, they must be allocated to page 0 */
	/*.econst             : > FLASHA,      PAGE = 0
	.switch             : > FLASHA ,     PAGE = 0*/

	/* Allocate IQ math areas: */
	IQmath              : > FLASH_E,		PAGE = 0                  /* Math Code */
	IQmathTables		: > IQTABLES,		PAGE = 0, TYPE = NOLOAD 
   

	IQmathTables2		: > IQTABLES2,		PAGE = 0, TYPE = NOLOAD 
	{
		IQmath_fpu32.lib<IQNexpTable.obj> (IQmathTablesRam)
	}
	IQmathTablesRam		: > FLASH_H,		PAGE = 1

	FPUmathTables		: > FPUTABLES,		PAGE = 0, TYPE = NOLOAD 	     

	/* Allocate 0x400 of XINTF Zone 7 to storing data */
	ZONE7DATA        	: > ZONE7B,			PAGE = 1

	/* .reset is a standard section used by the compiler.  It contains the */ 
	/* the address of the start of _c_int00 for C Code.   /*
	/* When using the boot ROM this section and the CPU vector */
	/* table is not needed.  Thus the default type is set here to  */
	/* DSECT  */ 
	.reset              : > RESET,			PAGE = 0, TYPE = DSECT
	vectors             : > VECTORS,		PAGE = 0, TYPE = DSECT

	csmpasswds          : > CSM_PWL,		PAGE = 0, TYPE = DSECT
	csm_rsvd            : > CSM_RSVD,		PAGE = 0, TYPE = DSECT

   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   	PAGE = 0, TYPE = NOLOAD
}

So our question are:

Does the CSM effect execution time of the code in Flash or unsecured memory?

How can we maintain the access speed of Flash when using CSM?

Best Regards,

Yi-Lin

0 Yi-Lin over 4 years ago in reply to Yi-Lin

Intellectual 545 points

Dear Hareesh,

We found a post that had similar situation of the CSM slowed down application execution time.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/254039/csm-slow-down-the-execution-of-the-application-reduces-the-speed-does-it-affect-the-clock-frecuency-with-tms320f28335

In that post, it said the problem can be solved by moving the InitFlash() function to secure memory area. We have checked our project and found our InitFlash() is mapped to L4 SARAM area unfortunately .

We are struggling on how to copy InitFlash() to secure zone. The system gave us an Initialized RAM Warning of "Warning: Because this program contains initialized RAM data it may run successfully under Code Composer Studio but not as a standalone system. If your Flash program requires initialized data in RAM, you will need to write Flash code to initialized RAM memory." when we tried to allocate the beginning of L0 SARAM(initflashfunc) for InitFlash(). Here is the memory configuration file we used:

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

	ZONE0		: origin = 0x004000, length = 0x001000		/* XINTF zone 0 */

    RAM_TEST    : origin = 0x008000, length = 0x000020		/* on-chip RAM block L0 specified for InitFlash */
	RAML0to4	: origin = 0x008020, length = 0x004FE0		/* on-chip RAM block L0~L5 */

	ZONE6		: origin = 0x100000, length = 0x100000		/* XINTF zone 6 */ 
	ZONE7A		: origin = 0x200000, length = 0x00FC00		/* XINTF zone 7 - program space */ 

	FLASH_E		: origin = 0x318000, length = 0x008000     /* FLASH_E: For system program storing in FLASH */
	FLASH_D		: origin = 0x320000, length = 0x008000     /* FLASH_D: For functions operating in flash */
	FLASH_C		: origin = 0x328000, length = 0x008000     /* FLASH_C: For functions operating in flash */
	FLASH_B		: origin = 0x330000, length = 0x008000     /* FLASH_B: For functions operating in ram (ramfuncs)*/
	FLASH_A		: origin = 0x338000, length = 0x007F80     /* FLASH A: Remain blank preventing from dead-lock @ 0x33FF80 ~ 0x33FFFF */


	CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
	BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
	CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
	OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
	ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */

	IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
	IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
	FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
	ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
	RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
	VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1     
	BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
	RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
	RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

	RAML5to6    : origin = 0x00D000, length = 0x002000     /* on-chip RAM block L6 */
	RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L7 */
	FPGA_RAM1_1	: origin = 0x204000, length = 0x000800     /* FPGA RAM 1.1, Store SDO object values */
	FPGA_RAM1_2	: origin = 0x204800, length = 0x000800     /* FPGA RAM 1.2, Store SDO object ECC values */
	FPGA_RAM2	: origin = 0x205000, length = 0x001000     /* FPGA RAM 2, Store CiA402 object values */
	FPGA_RAM3to4: origin = 0x206000, length = 0x002000     /* FPGA RAM 3&4, Store oscilloscope data */
	ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */

	FLASH_H		: origin = 0x300000, length = 0x008000     /* FLASH_H: For system data storing in FLASH */
	FLASH_G		: origin = 0x308000, length = 0x008000     /* FLASH_G: For the FLASH Default Specific Object values */
	FLASH_F		: origin = 0x310000, length = 0x008000     /* FLASH_F: For the FLASH Default CiA402 Object values */
	
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */

	.cinit              : > FLASH_E,		PAGE = 0
	.pinit              : > FLASH_E,		PAGE = 0
	.text               : > FLASH_C,		PAGE = 0
	.switch             : > FLASH_E,		PAGE = 0

	codestart           : > BEGIN,			PAGE = 0

	ramfuncs            : LOAD = FLASH_B//FLASHD, 
                         RUN = RAML0to4, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

	rts2800_lib_Flash	: > FLASH_E,		PAGE = 0
	{
		rts2800_fpu32.lib <*> (.text)
	}

	Flash28_API			:
	{
		-l Flash28335_API_V210.lib(.econst)
		-l Flash28335_API_V210.lib(.text)
	}
						 LOAD = FLASH_B,
						 RUN = RAML0to4,
                         LOAD_START(_Flash28_API_LoadStart),
                         LOAD_END(_Flash28_API_LoadEnd),
                         RUN_START(_Flash28_API_RunStart),
                         PAGE = 0

    initflashfunc		: > RAM_TEST,		PAGE = 0
	Auto_Tuning_Code	: > FLASH_D,		PAGE = 0

	Spec_Object			: > FPGA_RAM1_1,	PAGE = 1
	Spec_Object_ECC		: > FPGA_RAM1_2,	PAGE = 1
	CiA402Bkup_Object	: > FPGA_RAM2,		PAGE = 1
	Oci_Scop_Buff_SEC	: > FPGA_RAM3to4,	PAGE = 1

	DEF_SPEC_OBJ		: > FLASH_G,		PAGE = 1
	DEF_CIA402_OBJ		: > FLASH_F,		PAGE = 1
	/* Allocate uninitalized data sections: */
	.stack              : > RAMM1,			PAGE = 1
	.ebss               : > RAML5to6,		PAGE = 1
	.econst             : > FLASH_H,		PAGE = 1
	//.esysmem            : > HRAML0,		PAGE = 1//using this memory region will cause ILLEGAL_ISR() in APPL_GenerateMapping()
	.esysmem			: > RAMM1|RAML7,	PAGE = 1
	.sysmem				: > RAMM1|RAML7,	PAGE = 1
	/* Initalized sections go in Flash */
	/* For SDFlash to program these, they must be allocated to page 0 */
	/*.econst             : > FLASHA,      PAGE = 0
	.switch             : > FLASHA ,     PAGE = 0*/

	/* Allocate IQ math areas: */
	IQmath              : > FLASH_E,		PAGE = 0                  /* Math Code */
	IQmathTables		: > IQTABLES,		PAGE = 0, TYPE = NOLOAD 
   

	IQmathTables2		: > IQTABLES2,		PAGE = 0, TYPE = NOLOAD 
	{
		IQmath_fpu32.lib<IQNexpTable.obj> (IQmathTablesRam)
	}
	IQmathTablesRam		: > FLASH_H,		PAGE = 1

	FPUmathTables		: > FPUTABLES,		PAGE = 0, TYPE = NOLOAD 	     

	/* Allocate 0x400 of XINTF Zone 7 to storing data */
	ZONE7DATA        	: > ZONE7B,			PAGE = 1

	/* .reset is a standard section used by the compiler.  It contains the */ 
	/* the address of the start of _c_int00 for C Code.   /*
	/* When using the boot ROM this section and the CPU vector */
	/* table is not needed.  Thus the default type is set here to  */
	/* DSECT  */ 
	.reset              : > RESET,			PAGE = 0, TYPE = DSECT
	vectors             : > VECTORS,		PAGE = 0, TYPE = DSECT

	csmpasswds          : > CSM_PWL,		PAGE = 0, TYPE = DSECT
	csm_rsvd            : > CSM_RSVD,		PAGE = 0, TYPE = DSECT

   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   	PAGE = 0, TYPE = NOLOAD
}

Is there any step we neglect for changing the mapping area?

Is this the correct direction of solving our problem?

Best Regards,

Yi-Lin

0 Hareesh Janakiraman over 4 years ago in reply to Yi-Lin

TI__Guru* 95315 points

Yi,

Perhaps a slightly off-topic question. I presume you use an external EtherCAT slave IC, since TMS320F28335 does not have on-chip EtherCAT. Am I correct?

0 Hareesh Janakiraman over 4 years ago in reply to Hareesh Janakiraman

TI__Guru* 95315 points

Note that RAM blocks L0 to L3 are secure and L4 to L7 are unsecure. In your linker command file, you are combining four secure blocks (L0-L3) and one unsecure block (L4). This is not correct.

RAML0to4	: origin = 0x008000, length = 0x005000		/* on-chip RAM block L0~L5 */

Yi-Lin said:
Does the CSM effect execution time of the code in Flash or unsecured memory?

No.

Yi-Lin said:
How can we maintain the access speed of Flash when using CSM?

By configuring the flash for the correct number of wait-states. By default, flash memory runs with the maximum number of wait-states. If the wait-states are not configured correctly, your code will run slower. This has nothing to do with CSM. As mentioned in the other post, InitFlash needs to be run from secure RAM.

Yi-Lin said:
In that post, it said the problem can be solved by moving the InitFlash() function to secure memory area. We have checked our project and found our InitFlash() is mapped to L4 SARAM area unfortunately .

That is your problem. The flash is not configured for the correct (reduced) wait-states. Please look at the TI-supplied linker command file, F28335.cmd, in C:\ti\controlSUITE\device_support\f2833x\v142\DSP2833x_common\cmd for ideas. I have tried to attach it as a text file.

Yi-Lin said:
The system gave us an Initialized RAM Warning of "Warning: Because this program contains initialized RAM data it may run successfully under Code Composer Studio but not as a standalone system. If your Flash program requires initialized data in RAM, you will need to write Flash code to initialized RAM memory."

You need to resolve this. Otherwise, your application will only run through CCS, but not in standalone mode.

Fullscreen F28335.txt Download

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November  1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 1.  
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 1.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */


MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF      : origin = 0x310000, length = 0x008000     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */
   FLASHC      : origin = 0x328000, length = 0x008000     /* on-chip FLASH */
   FLASHA      : origin = 0x338000, length = 0x007F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA      PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHD, 
                         RUN = RAML0, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .ebss               : > RAML4       PAGE = 1
   .esysmem            : > RAMM1       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0      

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
   
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 1
   DMARAML5         : > RAML5,     PAGE = 1
   DMARAML6         : > RAML6,     PAGE = 1
   DMARAML7         : > RAML7,     PAGE = 1
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 1

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
   
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Yi-Lin over 4 years ago in reply to Hareesh Janakiraman

Intellectual 545 points

Dear Hareesh,

Sorry for the late reply. As we were trying to link to RAM_TEST area to CODE_SECTION pragma, this might be the reason that caused this problem. After we edited our link command file and copied the code we wish to run in RAM_TEST from FLASH. The project runs well in standalone mode.

Another question that we are curious about... Why the execution time of the code in FLASH will be affected by where the InitFlash() is located?

#define CPU_FRQ_150MHZ    1     // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT

void InitFlash(void)
{
   EALLOW;
   //Enable Flash Pipeline mode to improve performance
   //of code executed from Flash.
   FlashRegs.FOPT.bit.ENPIPE = 1;

   //                CAUTION
   //Minimum waitstates required for the flash operating
   //at a given CPU rate must be characterized by TI.
   //Refer to the datasheet for the latest information.
#if CPU_FRQ_150MHZ
   //Set the Paged Waitstate for the Flash
   FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;

   //Set the Random Waitstate for the Flash
   FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;

   //Set the Waitstate for the OTP
   FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
#endif

#if CPU_FRQ_100MHZ
   //Set the Paged Waitstate for the Flash
   FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;

   //Set the Random Waitstate for the Flash
   FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;

   //Set the Waitstate for the OTP
   FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
#endif
   //                CAUTION
   //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
   FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
   FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
   EDIS;

   //Force a pipeline flush to ensure that the write to
   //the last register configured occurs before returning.

   asm(" RPT #7 || NOP");
}

Many thanks for your reply.

Best Regards,

Yi-Lin

0 Hareesh Janakiraman over 4 years ago in reply to Yi-Lin

TI__Guru* 95315 points

You cannot configure flash through code that runs out of flash. That code must be run from RAM. That is why InitFlash() must be copied in RAM before execution.

0 Yi-Lin over 4 years ago in reply to Hareesh Janakiraman

Intellectual 545 points

Hi Hareesh,

As the InitFlash() located in L4 SARAM (unsecure zone) at the beginning in our project, why this can also cause the issue?

Thanks

Yi-Lin

+1 Hareesh Janakiraman over 4 years ago in reply to Yi-Lin

TI__Guru* 95315 points

The answer is in this post.

"The flash control registers are protected by the CSM. When you configure the flash wait-states, you access the flash control registers from your code. In addition, this code is supposed to be run in memory other than the flash (e.g., RAM) to avoid potential problems (i.e., you shouldn't configure the flash from code running from flash). Assuming that you followed this, you are copying the flash configuration code to RAM someplace and then running it. Is this copy being done to a CSM SECURE RAM block? If you run the flash config code from non-secure RAM, it will not be able to access the flash control registers and you will be running with excess wait-states. The secure RAM on F28335 are the L0 - L3 SARAM blocks (see the device datasheet)."

Short answer: InitFlash() must be run from secure RAM. L4 is not.

C2000™︎ microcontrollers

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TMS320F28335: Using Code Security Module(CSM) makes ISR execution time being longer