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DSP TMS320F28062 parallel-processing mode

user6088066
Prodigy 20 points

Hi:

I list some codes in my programme as below:

"

EWALLOW;

EPwm1Regs.CPMA.half.CMPA = u16_TempDuty1;//---Line1

EPwm1Regs.CPMB = u16_TempDuty2;//---Line2

EDIS;

"

Other ISR will  happen between line1 and line2.

By coincidence PWM counter reaches at zero or period during  this ISR,  the compare value of PWM1_A will be loaded and the value of PWM1_B still remains unchanged.

As a result, PWM_A and PWM_B pulses will probably be ON simultaneously----It is too dangerous.

Unfortunately, I can not set PWM1_A and PWM1_B to be DB(Dead Beat) mode in the programme.

So, my question is:

Line1 and Line2 can be set to be parallel-processing mode?

so, the compare register of PWM1_A and PWM1_B will be loaded at the same time. The ON simultaneous phenomenon between A and B will not happen.

Would you like to give me some advices?

Thank you for your help.

  • 0
    TI__Mastermind 22810 points

    Hello,

    In what ISR are lines1 and 2 within? A possible solution to this would be to update the compare values within an ISR that is synchronous to the PWM (such as an interrupt when EPWM1 TBCTR =  ZRO or PRD). You could still calculate the new values within another ISR but you want to make sure to update the actual values within an ISR that is synchronous to the PWM in order to avoid the situation that you described.

    user6088066 said:
    By coincidence PWM counter reaches at zero or period during  this ISR

    Would it be possible for you to scope this and check whether it happens during a zero or period event. Note that the CMPX values can be setup to have shadow loading at zero, period, or zero and period. For example, if the PWM counter reaches period during the ISR then you can update the compare values during a ZRO event only. This is another alternative to the suggestion I made above. 

    Best Regards,

    Marlyn