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TMS320F280048C-Q1: Running the full application code from RAM instead of Flash

Part Number: TMS320F280048C-Q1
Other Parts Discussed in Thread: C2000WARE

Hi,

   This is a continuation of the support case "">e2e.ti.com/.../3851239. As per the closure of the case, we were able to flash the device. However on further notice, it was observed that the RAM and Flash execution times are different (total activity time indicated by a GPIO Toggling). Flash its taking more time and loops went wrong. How can I copy the entire code from Flash to RAM after power-on and start execution from RAM to avoid any timing uncertainties. I am including the RAM linker file content in case its required. The default RAM linker file is modified as follows.


MEMORY
{
PAGE 0 :


BEGIN : origin = 0x000000, length = 0x000002

//RAMM0: origin = 0x0000F5, length = 0x00030B      // Default
RAMM0 : origin = 0x0000F5, length = 0x00060B       // Modified

RAMLS : origin = 0x008000, length = 0x003000         // Added

//RAMLS0 : origin = 0x008000, length = 0x000800     // Removed
//RAMLS1 : origin = 0x008800, length = 0x000800     // Removed
//RAMLS2 : origin = 0x009000, length = 0x000800     // Removed
//RAMLS3 : origin = 0x009800, length = 0x000800     // Removed
//RAMLS4 : origin = 0x00A000, length = 0x000800     // Removed

RESET : origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x0000F3 

//RAMM1 : origin = 0x000400, length = 0x000400       // Default
RAMM1 : origin = 0x000700, length = 0x000200         // Modified

//RAMLS5 : origin = 0x00A800, length = 0x000800      // Default
//RAMLS6 : origin = 0x00B000, length = 0x000800      // Default

RAMLS5 : origin = 0x00A800, length = 0x000B00        // Modified
RAMLS6 : origin = 0x00B300, length = 0x000500        // Modified
RAMLS7 : origin = 0x00B800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x002000
}


SECTIONS
{
codestart : > BEGIN, PAGE = 0
.TI.ramfunc : > RAMM0 PAGE = 0
.text : >>RAMM0 | RAMLS , PAGE = 0                            // Modified
//.text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0  // Default
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM1, PAGE = 1
.ebss : > RAMLS5, PAGE = 1
.econst : > RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1

ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
}

Thanks and Regards

   Karthik R

  • Hi Karthik.

    You will need to use the Flash linker command file. You will see the following lines in the linker command file for loading code code to RAM from Flash.

    #if defined(__TI_EABI__)
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS0,
    LOAD_START(RamfuncsLoadStart),
    LOAD_SIZE(RamfuncsLoadSize),
    LOAD_END(RamfuncsLoadEnd),
    RUN_START(RamfuncsRunStart),
    RUN_SIZE(RamfuncsRunSize),
    RUN_END(RamfuncsRunEnd),
    PAGE = 0, ALIGN(4)
    #else
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS0,
    LOAD_START(_RamfuncsLoadStart),
    LOAD_SIZE(_RamfuncsLoadSize),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRunSize),
    RUN_END(_RamfuncsRunEnd),
    PAGE = 0, ALIGN(4)
    #endif

    Then specific functions or all functions can be placed in RAM. See the following compiler optimizing guide and look for "ramfunc" in the document for these 2 options.

    https://www.ti.com/lit/spru514

    Thanks,

    Ashwini

  • Hi Aswini,

     Thanks for the response and sorry for the late reply due to holidays. I have briefly gone through the compiler user guide. Please see the following doubts.

    1) In the above mail, the instructions under the #if and #else conditions are identical ryt. So why the #if / #else condition is introduced ?

    2) I have added the --ramfunc==on in the compiler flag and tried to build but it is returning "code cannot be fit in the memory..the section contains a call site that requires a trampoline that can't be generated for this section..." pointing to ".TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS0,...."

     I had raised a query for similar error in the debugging from RAM operation (https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/979405/launchxl-f280049c-memory-linking-error). It was not fully closed but had suggested a workaround which I applied as follows.

    3) So I have modified the flash linker file as follows

    MEMORY
    {
    PAGE 0 :


    BEGIN : origin = 0x000000, length = 0x000002

    RAMM0: origin = 0x0000F5, length = 0x00030B

    RAMLS : origin = 0x008000, length = 0x003000 

    .....

    #else
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS,
    LOAD_START(_RamfuncsLoadStart),

    now its throwing error mentioning code cannot be fit in "FLASH_BANK0_SEC1"

      Please advice how to proceed.

    Thanks and Regards

        Karthik R

  • Hi Karthik,

    In the above mail, the instructions under the #if and #else conditions are identical ryt. So why the #if / #else condition is introduced ?

    The symbol names are a bit different for EABI and COFF format. The #if associates symbols that EABI uses and the #else associates symbol names that COFF uses which begin with an underscore.

    now its throwing error mentioning code cannot be fit in "FLASH_BANK0_SEC1"

    In the error the output will indicate the size of the code that did not fit. Likely this is more than the FLASH_BANK0_SEC1 size and hence the error. You will need to allocate more Flash.

    Also, going forward some more suggestions:

    1. Please make sure the code is compiler with Optimization -O2 at least for good performance.

    2. In terms of system design, it will be helpful to do an analysis and check which pieces of code are timing critical and selectively have those loaded to RAM instead of the entire  application. As the application grows, it may not all fit in RAM which is 100KB vs Flash which is 256KB.

    Thanks,

    Ashwini 

  • Hi Aswini,

      Thanks for the response. Please see the error messages reported for the test-cases mentioned in the previous mail.

      1) As given in the compiler user guide, I have added the "--ramfunc=on" flag to copy all the functions to ramfunc in the Compiler flag set.

         But while building the default flash linker file following error was thrown.
     
    <Linking>
    "../28004x_generic_flash_lnk.cmd", line 116: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. run placement with alignment/blocking fails for section ".TI.ramfunc" size 0x1a1epage 0. Available memory ranges:
    RAMLS0 size: 0x800 unused: 0x800 max hole: 0x800 
    "../28004x_generic_flash_lnk.cmd", line 116: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. load placement with alignment/blocking fails for section ".TI.ramfunc" size 0x1a1epage 0. Available memory ranges:
    FLASH_BANK0_SEC1 size: 0x1000 unused: 0x1000 max hole: 0x1000
     
    We had observed similar errors earlier, while debugging from RAM. So we had modified the RAM linker filer and then debugging from RAM was succesful. So we made similar modifications in the Flash linker file as follows.
     
    2) So in the Flash linker file I have changed to this
     
    MEMORY
    {
    PAGE 0 :
    /* BEGIN is used for the "boot to Flash" bootloader mode */

    BEGIN : origin = 0x080000, length = 0x000002
    RAMM0 : origin = 0x0000F3, length = 0x00030D

    RAMLS : origin = 0x008000, length = 0x003000

    RESET : origin = 0x3FFFC0, length = 0x000002

    /* Flash sectors */
    /* BANK 0 */
    FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
    .....
     
    #if defined(__TI_EABI__)
    .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .bss : > RAMLS5, PAGE = 1
    .bss:output : > RAMLS6, PAGE = 1
    .bss:cio : > RAMLS, PAGE = 0
    .data : > RAMLS5, PAGE = 1
    ......
    #else
    .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .ebss : > RAMLS5, PAGE = 1
    .esysmem : > RAMLS5, PAGE = 1
    .cio : > RAMLS, PAGE = 0
    .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)

    ...
     
    #if defined(__TI_EABI__) 
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS,
    ......
    #else 
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS,
    .....
    #endif

    }
     
    Now its again throwing following error
     
    <Linking>
    "../28004x_generic_flash_lnk.cmd", line 113: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. load placement with alignment/blocking fails for section ".TI.ramfunc" size 0x1a1epage 0. Available memory ranges:
    FLASH_BANK0_SEC1 size: 0x1000 unused: 0xad7 max hole: 0xad4 
    error #10010: errors encountered during linking; "led_ex1_blinky.out" not built
     
    3) So as per your suggestion in the previous mail to increase the Flash memory, following modifications was done in the flash linker file.
     
     
    MEMORY
    {
    PAGE 0 :
    /* BEGIN is used for the "boot to Flash" bootloader mode */

    BEGIN : origin = 0x080000, length = 0x000002
    RAMM0 : origin = 0x0000F3, length = 0x00030D

    RAMLS : origin = 0x008000, length = 0x003000

    RESET : origin = 0x3FFFC0, length = 0x000002

    /* Flash sectors */
    /* BANK 0 */
    FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
    FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x002000 /* on-chip Flash */
    //FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
    FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
    ......

    /* BANK 1 */
    FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
    .......
    FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */

    // FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    PAGE 1 :

    BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
    RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
    // RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    RAMLS5 : origin = 0x00A800, length = 0x000800
    RAMLS6 : origin = 0x00B000, length = 0x000800
    RAMLS7 : origin = 0x00B800, length = 0x000800

    RAMGS0 : origin = 0x00C000, length = 0x002000
    RAMGS1 : origin = 0x00E000, length = 0x002000
    RAMGS2 : origin = 0x010000, length = 0x002000
    RAMGS3 : origin = 0x012000, length = 0x001FF8
    // RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    }


    SECTIONS
    {
    codestart : > BEGIN, PAGE = 0, ALIGN(4)
    .text : >> FLASH_BANK0_SEC3 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4)
    //.text : >> FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4)
    .cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    .stack : > RAMM1, PAGE = 1

    #if defined(__TI_EABI__)
    .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .bss : > RAMLS5, PAGE = 1
    .bss:output : > RAMLS6, PAGE = 1
    .bss:cio : > RAMLS, PAGE = 0
    .data : > RAMLS5, PAGE = 1
    .sysmem : > RAMLS5, PAGE = 1
    /* Initalized sections go in Flash */
    .const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
    #else
    .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
    .ebss : > RAMLS5, PAGE = 1
    .esysmem : > RAMLS5, PAGE = 1
    .cio : > RAMLS, PAGE = 0
    .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
    #endif

    ramgs0 : > RAMGS0, PAGE = 1
    ramgs1 : > RAMGS1, PAGE = 1


    #if defined(__TI_EABI__)
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS,
    ......
    #else
    .TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
    RUN = RAMLS,
    ......
    #endif

    }

     Now there were no errors in building or flashing but now the code is not working properly. There is no GPIO output toggling. (Before this modification, we were able to get the GPIO toggling but at twice the frequency. The GPIO specifies the activity time of our application code. In the debug from RAM mode it was taking x time and after flashing with default linker file it was taking 2x time). 
     
    4) In terms of system design, it will be helpful to do an analysis and check which pieces of code are timing critical and selectively have those loaded to RAM instead of the entire  application. 
    Yes, I understand but our application and the procedure followed at my working place demands execution only from RAM.
     
      Please advice how to proceed.

    Thanks n Regards,

           Karthik R

  • Hi Karthik,

    If you set breakpoints where GPIO is initialized  and where GPIO toggles are those breakpoints being taken? After loading application and entering main you can set breakpoints and step through code to make sure the functions are being correctly copied and executed from RAM.

    Thanks,

    Ashwini

  • Hi Aswini,

      In flash mode, we can put breakpoints...?? Sorry, I didn't knew that.

       Is there no solid examples which simply copies entrie flash content to ram n execute form it...?

    Thanks and Regards

      Karthik R

  • Hi Karthik,

    Yes, you can use Hardware breakpoints to debug code in Flash and RAM. In your initialization code, you should have following lines that copy code to RAM.

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

    Run past this source line. You can then set HWBP at the function you want to debug which has the GPIO toggling.

    I don't believe we have an application that copies entire code to RAM. However the steps above should allow you to debug the issue.

    Thanks,

    Ashwini

  • Hi Aswini,

       Thanks for the information regarding the same. It was quite new to me. Infact I am not that versed in modifying default settings of linkers and script unless the condition demands it. I am confused whether we need to proceed with breakpoint insertion n all. GPIO setting is my first instruction inside the ISR which is not happening means there is something fundamentally wrong.

       I have repeated the entire process once again. For both modes, "--ramfunc=on" flag is added in the compiler flag options.

       While debugging from RAM, the DSC is behaving as expected (by monitoring the GPIO).

       After Flashing, now GPIO is not toggling at all. Can you please see whats wrong with the linker files. I believe this should throw light into the fundamental thing which is wrong. I have included the complete linker file contents.

    _____________________________

    RAM LINKER FILE CONTENT

    ______________________________

    MEMORY

    {

    PAGE 0 :

    /* BEGIN is used for the "boot to SARAM" bootloader mode */

    BEGIN : origin = 0x000000, length = 0x000002

    RAMM0 : origin = 0x0000F5, length = 0x00060B

    RAMLS0 : origin = 0x008000, length = 0x000800

    // RAMLS1 : origin = 0x008800, length = 0x000800

    // RAMLS2 : origin = 0x009000, length = 0x000800

    // RAMLS3 : origin = 0x009800, length = 0x000800

    // RAMLS4 : origin = 0x00A000, length = 0x000800

    RAMLS1234 : origin = 0x008800, length = 0x002000

    RESET : origin = 0x3FFFC0, length = 0x000002

    PAGE 1 :

    BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */

    RAMM1 : origin = 0x000700, length = 0x000100 /* on-chip RAM block M1 */

    RAMLS5 : origin = 0x00A800, length = 0x000800

    RAMLS6 : origin = 0x00B000, length = 0x000800

    RAMLS7 : origin = 0x00B800, length = 0x000800

    RAMGS0 : origin = 0x00C000, length = 0x002000

    RAMGS1 : origin = 0x00E000, length = 0x002000

    RAMGS2 : origin = 0x010000, length = 0x002000

    RAMGS3 : origin = 0x012000, length = 0x002000

    }

    SECTIONS

    {

    codestart : > BEGIN, PAGE = 0

    .TI.ramfunc : > RAMLS1234 PAGE = 0

    .text : >>RAMM0 | RAMLS0 | RAMLS1234, PAGE = 0

    //.TI.ramfunc : > RAMM0 PAGE = 0

    //.text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0

    .cinit : > RAMM0, PAGE = 0

    .pinit : > RAMM0, PAGE = 0

    .switch : > RAMM0, PAGE = 0

    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    .stack : > RAMM1, PAGE = 1

    .ebss : > RAMLS5, PAGE = 1

    .econst : > RAMLS5, PAGE = 1

    .esysmem : > RAMLS5, PAGE = 1

    ramgs0 : > RAMGS0, PAGE = 1

    ramgs1 : > RAMGS1, PAGE = 1

    }

    ____________________

    FLASH LINKER FILE

    ____________________

    MEMORY

    {

    PAGE 0 :

    /* BEGIN is used for the "boot to Flash" bootloader mode */

    BEGIN : origin = 0x080000, length = 0x000002

    RAMM0 : origin = 0x0000F5, length = 0x00060B

    RAMLS0 : origin = 0x008000, length = 0x000800

    // RAMLS1 : origin = 0x008800, length = 0x000800

    // RAMLS2 : origin = 0x009000, length = 0x000800

    // RAMLS3 : origin = 0x009800, length = 0x000800

    // RAMLS4 : origin = 0x00A000, length = 0x000800

    RAMLS1234 : origin = 0x008800, length = 0x002000

    RESET : origin = 0x3FFFC0, length = 0x000002

    /* Flash sectors */

    /* BANK 0 */

    FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */

    FLASH_BANK0_SEC1n2 : origin = 0x081000, length = 0x002000 /* on-chip Flash */

    //FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */

    //FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */

    /* BANK 1 */

    FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */

    FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */

    PAGE 1 :

    BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */

    RAMM1 : origin = 0x000700, length = 0x000100 /* on-chip RAM block M1 */

    RAMLS5 : origin = 0x00A800, length = 0x000800

    RAMLS6 : origin = 0x00B000, length = 0x000800

    RAMLS7 : origin = 0x00B800, length = 0x000800

    RAMGS0 : origin = 0x00C000, length = 0x002000

    RAMGS1 : origin = 0x00E000, length = 0x002000

    RAMGS2 : origin = 0x010000, length = 0x002000

    RAMGS3 : origin = 0x012000, length = 0x002000

    }

    SECTIONS

    {

    codestart : > BEGIN, PAGE = 0, ALIGN(4)

    .text : >>FLASH_BANK0_SEC1n2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4)

    //.text : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4)

    .cinit : > FLASH_BANK0_SEC1n2, PAGE = 0, ALIGN(4)

    .pinit : > FLASH_BANK0_SEC1n2, PAGE = 0, ALIGN(4)

    .switch : > FLASH_BANK0_SEC1n2, PAGE = 0, ALIGN(4)

    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    .stack : > RAMM1, PAGE = 1

    .ebss : > RAMLS5, PAGE = 1

    .esysmem : > RAMLS5, PAGE = 1

    .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)

    ramgs0 : > RAMGS0, PAGE = 1

    ramgs1 : > RAMGS1, PAGE = 1

    .TI.ramfunc : {} LOAD = FLASH_BANK0_SEC1n2,

    RUN = RAMLS1234,

    LOAD_START(_RamfuncsLoadStart),

    LOAD_SIZE(_RamfuncsLoadSize),

    LOAD_END(_RamfuncsLoadEnd),

    RUN_START(_RamfuncsRunStart),

    RUN_SIZE(_RamfuncsRunSize),

    RUN_END(_RamfuncsRunEnd),

    PAGE = 0, ALIGN(4)

    }

    Can you please see what's wrong with these files

    Thanks. 

          Karthik R

  • Hi Karthik,

    I could not spot any issues with the Flash linker command file which is what you will need (RAM linker command file does not need to be included in your project). You can also refer to the linker command files in C2000Ware in device_support - "28004x_generic_flash_lnk.cmd"

    I would recommend that you use the steps I indicated above to debug and check that all you code is being copied to RAM as expected and the ISRs are being triggered. If the ISR isbeing triggered as expected - then maybe the GPIO configuration did not get executed as expected.

    Thanks,
    Ashwini