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F28M36P63C2: Shared RAM initialization problem after watchdog reset

Markus Tamas
Intellectual 620 points
Part Number: F28M36P63C2

Hi,

I have a problem with initializing some shared RAM blocks with the M3 subsystem after a watchdog reset.

This is my code. It works after a power on reset but gets stuck in the while loop after a watchdog reset.

RAMMReqSharedMemAccess(0xF0, SX_M3MASTER);

// HWREG(RAM_CONFIG_BASE + RAM_O_MSXMSEL) read returns 0x0F

HWREG(RAM_CONFIG_BASE + RAM_O_MSXRTESTINIT1) |= 0x5500;
while((HWREG(RAM_CONFIG_BASE + RAM_O_MSXRINITDONE1) & 0x5500) != 0x5500)
{
}

Do you have any idea why? Thanks in advance!

Best regards,
Tamas

  • 0
    TI__Mastermind 31525 points

    Hi,

    We have assigned your query to the module expert. You will get a response soon.

    Thanks and Regards,

    Veena

  • 0 in reply to Veena Kamath
    Intellectual 620 points

    Hi Veena,
    thank you and regards,
    Tamas

  • +1 in reply to Markus Tamas
    TI__Guru 71815 points

    Markus,

    Can you comment if the watchdog reset is from the master(M3) subsystem or from the Control system?  If this is from the CNMIWD then that will not reset any locks on the master side(if they have been done).  You would also need to check if in your code after the above there is any change to the write protection of this memory or the TESTINIT1 register itself.  If so, then either the write to the register or the init of the memory would be blocked, hence we can never get an init complete.

    If the watchdog is on the master side, that should activate the external XRSn signal, and completely reset the whole device and be equivalent to a power on reset.  Since you mention the different resets have different behavior I think some aspect of the above must be the case.

    Let me know what you find, and we can go from there.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Intellectual 620 points

    Hello Matthew,

    I forgot to disable the write protection. It did not cause any problem after power on reset and the error went unnoticed. This code is working even after a M3 watchdog reset:

        unsigned long tmp = HWREG(SYSCTL_MWRALLOW);
    HWREG(SYSCTL_MWRALLOW) = 0xA5A5A5A5;

    HWREG(RAM_CONFIG_BASE + RAM_O_MSXRTESTINIT1) |= init_bits;

    HWREG(SYSCTL_MWRALLOW) = tmp;

    while ((HWREG(RAM_CONFIG_BASE + RAM_O_MSXRINITDONE1) & init_bits) != init_bits) {
    }

    Thank you for your help!

    Best regards,
    Tamas