Hello, expert:
I see about tformat encoder page 13 of the document (www.ti.com.cn/.../tidue74c.pdf has the description "In this state,CLB generates a number of clock cycles corresponding to the data to be sent by encoder -- which in turn is dependent onthe command transmitted. Once the number of SPI CLKs generated matches the data bits transmitted by encoder, the transaction is complete and FSM1 moves back to IDLE state waiting for next operation to be Triggered. "So how is the corresponding clock cycle triggered?If my clock frequency is correct, how can I modify the program to get my clock cycle number correct?
Best Regards
Johnson Alanl