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TMS320F28386D: CMTOCPU1INTCTL register explanation

Part Number: TMS320F28386D


I am struggling to understand the difference between the CMTOCPU1NMICTL and CMTOCPU1INTCTL, or rather not understanding hte later.

I do understand that the first register allows to configure whether or not the CM a NMI WDRST fires a NMI on the CPU1.

However, for the second register, where do those interrupts are fired on CPU1 ? Can't seem to find any of them defined in the peripheral interrupts table.

Best regards,