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TMS320F280023C: Question about CAN error frame

Part Number: TMS320F280023C

Dear team:

When my customer tested the can_ex1_loopback routine on two 80pin and 60pin chips (CAN: GPIO4、GPIO5), they found that after shielding the following statement, the program can run normally on the 80PIN chip, but it will not work on the 60PIN chip. An error frame occurred.

But if the original program is used, both boards can send can messages normally without error frames.

// txMsgData[0] = 0x01;
// txMsgData[1] = 0x02;

Where the routine is modified:

1. Modify in board.c: CAN pin + send 8 bytes + 250K baud rate.

2. The chip uses the internal crystal oscillator OSC2, the configuration is as follows:

//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          10000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 30 (IMULT) / (2 (REFDIV) * 3 (ODIV) * 1(SYSDIV))
//

#define DEVICE_SETCLOCK_CFG          (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(30) | \
                                      SYSCTL_REFDIV(1) | SYSCTL_ODIV(3) | \
                                      SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                      SYSCTL_DCC_BASE_0)

//
// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 30) / (1 * 3 * 1))


//
// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

In addition, the test found that testing the code on another 48-pin chip, the effect was even worse, and there was only one frame of correct message occasionally.

Why is this?

Best regards

  • Hi,

    Thanks for your question, action items highlighted in bold below:

    From a software perspective, there should be no difference between the three chips (80, 60, and 48).

    1. Can you provide info on what was changed between the 3 chips in software?

    Basically, if there is no change in software between the three chips, then this is most likely a hardware issue, related to something different on each board that is also connected to the GPIO4/GPIO5 pins.

    2. Can you request the schematic of GPIO4 and GPIO5 pins on all three chips' boards (80,60,48)?

    Please note: I will be on holiday for the next two weeks will be unable to support till I return on January 3rd, 2022.

    Regards,

    Vince