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TMS320F28062: Question about SPI

Green Deng
Expert 4490 points
Part Number: TMS320F28062

Dear team:

My customer uses two F28062 chips for engineering development. Both chips use CPUtimer to define a task with a running cycle of 1ms. The entire program is executed sequentially and then waits for the main interrupt to execute again. Among them, the master also has a higher priority interrupt for high-frequency calculations, while the slave does not have this interrupt, only a 1ms interrupt.

SPI is used for communication between the two chips, and there will be about 30 16-bit data for interaction between the master and slave. That is, SPI dual-computer communication is realized in a program that runs periodically, receiving interrupts and sending without interrupts.

How to set up to ensure that 30 16-bit data SPI transceivers can be sent and received under the premise that the cycle stability does not affect other functions and real-time performance, and the transmission must also ensure the same periodicity?

Best regards

  • +1
    TI__Mastermind 25311 points

    Hi Green,

    Green Deng said:
    How to set up to ensure that 30 16-bit data SPI transceivers can be sent and received under the premise that the cycle stability does not affect other functions and real-time performance, and the transmission must also ensure the same periodicity?

    To minimize the CPU loading required to carry out the SPI receive and transmit operation, you can leverage the DMA of the device to do the data movement between memory and SPI buffers. It will only take a few cycles to setup the DMA initially.

    You should also configure the speed of the SPI such that the 30 16-bit data transfers complete in the required timeframe. The SPI has a 4-level transmit/receive FIFO which will help reduce the time required to service the SPI.