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TMS320F28065: Missing clock detect circuit

Part Number: TMS320F28065

Hi team,

My customer is testing TMS320F28065 and got some problems.

Problem:

MCU was reset by "Missing-Clock-Detect circuit" in their test.

They investigated and found the abnormal clock  for 400ns.

Environmental:

External 20MHz Oscillator, using 90MHz by PLL

Questions:

1. Do you have the equivalent circuit for Missing-Clock-Detect Circuit?

2. Does Missing-Clock-Detect circuit have the functions other than Missing clock? e.g. over voltage...

3. Does Missing Clock Detect circuit keep abnormality by latch-up?

 

best regards,

Yuto

  • Yuto,

    We give a description of how the missing clock detect logic works in the TRM https://www.ti.com/lit/spruh18 starting on page 88.  Essentially the clock input to the device drives a counter, and at the same time a reference clock from the PLL drives another counter.  When the main clock counter overflows it will reset the PLL counter.  If the clock goes missing then the PLL counter will not get reset and when it overflows it will issue the missing clock detect.

    Per above missing clock detect is only that function, there is no monitor of voltage of the X-tal.  Since the X-tal is a circuit driven from the MCU, I'm not certain how there could be an overvoltage unless there was some external influence.

    Latch up, if it were the root cause of an issue, would be hard to say what logic fails.  This would assume that a device pin saw > diode above VDDIO or I suppose above VDD if we are talking about X1/X2 specifically.

    Does customer know the cause of the abnormality seen on the X1 input?

    Best,
    Matthew

  • Thanks, Pate

    We can see the block diagram on your link(page 88).

    1. But do you have the schematics or equivalent circuit of Missing-Clock-Detect(MCD) circuit?

    2. When clock has an error, we can also see the voltage error with VDDIO.

    According to this, is there a possibility that  MCD circuit is latched up and keeps the error?

     

    Yuto 

  • Yuto,

    We don't have an equivalent circuit to share, what you see is how the device is built per VSDL.  The counters are all logic in the VDD domain.  Has the customer tried to disable the missing clock detect logic with the MCLKOFF bit in the PLLSTS register and note if the action goes away?

    It may be that the over-voltage even has created a latch-up event in the X-tal circuit, does the customer observe normal X-tal activity after the missing clock/spur issue occurs to the system, but the missing clock detect logic is still reporting an issue?  I believe there is a sequence to recover from MCD outlined in the TRM, I would make sure this is being followed.

    Best,

    Matthew