C2000WARE-MOTORCONTROL-SDK: LAUNCHXL-F280025C dual motor driver DRV8323RS issue

You must assign and configure the ADC, CMPSS for the second motor according to the connection of LUANCHXL-F280025C and BOOSTXL-DRV8323RS. Don't use the same CMPSS input for both motor 1 and motor 2. Also you need to change the XBAR for linking the output of CMPSS and nFAULT to the related ePWM modules for motor 2.

Follow the lab user's guide to disconnect and reconnect some pins on LUANCHXL-F280025C and BOOSTXL-DRV8323RS.

Hello and thank you for your assistance.

I have configured both motors, these are the values I am using, perhaps you can point out if you think any are incorrect:

/// Define which PWM module to use
#define MTR1_PWM_U_BASE         EPWM1_BASE
#define MTR1_PWM_V_BASE         EPWM2_BASE
#define MTR1_PWM_W_BASE         EPWM3_BASE

/// Comparator
#define MTR1_CMPSS_U_BASE       CMPSS1_BASE
#define MTR1_CMPSS_V_BASE       CMPSS3_BASE
#define MTR1_CMPSS_W_BASE       CMPSS1_BASE

//#define MTR1_XBAROUTPUT         XBAR_OUTPUT7

//! \brief Defines the gpio for enabling Power Module
#define MTR1_GATE_EN_GPIO       29

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR1_PM_nFAULT_GPIO     34

//! \brief Defines the gpio for calibration
#define MTR1_GATE_CAL_GPIO      27

//------------------------------------------------------------------------------
// ADC
// Three-shunt
#define MTR1_ADC_TIGGER_SOC     ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA
#define MTR1_ADC_I_SAMPLEWINDOW     14
#define MTR1_ADC_V_SAMPLEWINDOW     20

#define MTR1_IU_ADC_BASE        ADCA_BASE               // ADCA-A11*/C0
#define MTR1_IV_ADC_BASE        ADCC_BASE               // ADCC-A14/C4*
#define MTR1_IW_ADC_BASE        ADCC_BASE               // ADCC-A15/C7*
#define MTR1_VU_ADC_BASE        ADCA_BASE               // ADCA-A6*
#define MTR1_VV_ADC_BASE        ADCA_BASE               // ADCC-A3*/C5
#define MTR1_VW_ADC_BASE        ADCC_BASE               // ADCA-A2/C9*
#define MTR1_VDC_ADC_BASE       ADCC_BASE               // ADCC-C6*

#define MTR1_IU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A11*/C0
#define MTR1_IV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A14/C4*
#define MTR1_IW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A15/C7*
#define MTR1_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A6*
#define MTR1_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCC-A3*/C5
#define MTR1_VW_ADCRES_BASE     ADCCRESULT_BASE         // ADCA-A2/C9*
#define MTR1_VDC_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-C6*

#define MTR1_IU_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCA-A11*/C0
#define MTR1_IV_ADC_CH_NUM      ADC_CH_ADCIN4           // ADCC-A14/C4*
#define MTR1_IW_ADC_CH_NUM      ADC_CH_ADCIN7           // ADCC-A15/C7*
#define MTR1_VU_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCA-A6*
#define MTR1_VV_ADC_CH_NUM      ADC_CH_ADCIN3           // ADCC-A3*/C5
#define MTR1_VW_ADC_CH_NUM      ADC_CH_ADCIN9           // ADCA-A2/C9*
#define MTR1_VDC_ADC_CH_NUM     ADC_CH_ADCIN6           // ADCC-C6*

#define MTR1_IU_ADC_SOC_NUM     ADC_SOC_NUMBER1         // ADCA-A11*/C10-SOC1-PPB1
#define MTR1_IV_ADC_SOC_NUM     ADC_SOC_NUMBER1         // ADCC-A14/C4* -SOC1-PPB1
#define MTR1_IW_ADC_SOC_NUM     ADC_SOC_NUMBER2         // ADCC-A15/C7* -SOC2-PPB2
#define MTR1_VU_ADC_SOC_NUM     ADC_SOC_NUMBER4         // ADCA-A6*     -SOC4
#define MTR1_VV_ADC_SOC_NUM     ADC_SOC_NUMBER5         // ADCC-A3*/C5  -SOC5
#define MTR1_VW_ADC_SOC_NUM     ADC_SOC_NUMBER5         // ADCA-A2/C9*  -SOC5
#define MTR1_VDC_ADC_SOC_NUM    ADC_SOC_NUMBER6         // ADCC-C6*     -SOC6

#define MTR1_IU_ADC_PPB_NUM     ADC_PPB_NUMBER1         // ADCA-A11*/C10-SOC1-PPB1
#define MTR1_IV_ADC_PPB_NUM     ADC_PPB_NUMBER1         // ADCC-A14/C4* -SOC1-PPB1
#define MTR1_IW_ADC_PPB_NUM     ADC_PPB_NUMBER2         // ADCC-A15/C7*- SOC2-PPB2

// only for datalog and PWMDAC
#define MTR1_IU_ADCRESLT        MTR1_IU_ADCRES_BASE + ADC_O_RESULT1     // ADCA-A11*/C10-SOC1
#define MTR1_IV_ADCRESLT        MTR1_IV_ADCRES_BASE + ADC_O_RESULT1     // ADCC-A14/C4* -SOC1
#define MTR1_IW_ADCRESLT        MTR1_IW_ADCRES_BASE + ADC_O_RESULT2     // ADCC-A15/C7*- SOC2

#define MTR1_VU_ADCRESLT        MTR1_VU_ADCRES_BASE + ADC_O_RESULT4     // ADCA-A6*     -SOC4
#define MTR1_VV_ADCRESLT        MTR1_VV_ADCRES_BASE + ADC_O_RESULT5     // ADCC-A3*/C5  -SOC5
#define MTR1_VW_ADCRESLT        MTR1_VW_ADCRES_BASE + ADC_O_RESULT5     // ADCA-A2/C9*  -SOC5
#define MTR1_VDC_ADCRESLT       MTR1_VDC_ADCRES_BASE + ADC_O_RESULT6    // ADCC-C6*     -SOC6

//------------------------------------------------------------------------------
// interrupt
#define MTR1_ADC_INT_BASE       ADCC_BASE               // ADCC-C6  -SOC6
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER1         // ADCC_INT1-SOC6
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER6         // ADCC_INT1-SOC6

#define MTR1_PIE_INT_NUM        INT_ADCC1               // ADCC_INT1-SOC6
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT1      // ADCC_INT1-CPU_INT1
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP1    // ADCC_INT1-CPU_INT1

//------------------------------------------------------------------------------
// CMPSS
#define MTR1_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_1    // CMPSS1-A11
#define MTR1_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // CMPSS1-A11, N/A

#define MTR1_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // CMPSS3-C4
#define MTR1_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // CMPSS3-C4

#define MTR1_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_1    // CMPSS1-C7, N/A
#define MTR1_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // CMPSS1-C7

#define MTR1_IU_CMPHP_MUX       1                            // CMPSS1-A11
#define MTR1_IU_CMPLP_MUX       1                            // CMPSS1-A11

#define MTR1_IV_CMPHP_MUX       4                            // CMPSS3-C4
#define MTR1_IV_CMPLP_MUX       4                            // CMPSS3-C4

#define MTR1_IW_CMPHP_MUX       3                            // CMPSS1-C7
#define MTR1_IW_CMPLP_MUX       3                            // CMPSS1-C7

#define MTR1_CMPSS_DACH_VALUE   2048+1024+512
#define MTR1_CMPSS_DACL_VALUE   2048-1024-512

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR1_XBAR_TRIP_ADDRL    XBAR_O_TRIP7MUX0TO15CFG
#define MTR1_XBAR_TRIP_ADDRH    XBAR_O_TRIP7MUX16TO31CFG

#define MTR1_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX00_CMPSS1_CTRIPH       // CMPSS1-HP
#define MTR1_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L  // CMPSS3-HP&LP
#define MTR1_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX01_CMPSS1_CTRIPL       // CMPSS1-LP
//
#define MTR1_IU_XBAR_MUX        XBAR_MUX00          // CMPSS1-HP
#define MTR1_IV_XBAR_MUX        XBAR_MUX04          // CMPSS3-HP&LP
#define MTR1_IW_XBAR_MUX        XBAR_MUX01          // CMPSS1-LP
//
#define MTR1_XBAR_INPUT1        XBAR_INPUT1
#define MTR1_TZ_OSHT1           EPWM_TZ_SIGNAL_OSHT1

#define MTR1_XBAR_TRIP          XBAR_TRIP7
#define MTR1_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN7

//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR1_PWM_DBFED_CNT      5           // 50ns

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR1_PWM_DBRED_CNT      5           // 50ns

//------------------------------------------------------------------------------
/// Motor 2 @todo verify
#define MTR2

#define MTR2_STARTING_SPEED_REF_HZ     40.0f
#define MTR2_STARTING_VOLTAGE_REF_V    0.0f

#define MTR2_PWM_U_BASE         EPWM7_BASE
#define MTR2_PWM_V_BASE         EPWM4_BASE
#define MTR2_PWM_W_BASE         EPWM5_BASE

#define MTR2_CMPSS_U_BASE       CMPSS2_BASE
#define MTR2_CMPSS_V_BASE       CMPSS2_BASE
#define MTR2_CMPSS_W_BASE       CMPSS4_BASE

//! \brief Defines the gpio for enabling Power Module
#define MTR2_GATE_EN_GPIO       24

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR2_PM_nFAULT_GPIO     41

//! \brief Defines the gpio for calibration
#define MTR2_GATE_CAL_GPIO      27

//------------------------------------------------------------------------------
// ADC
// Three-shunt
#define MTR2_ADC_TIGGER_SOC     ADC_TRIGGER_EPWM7_SOCA  // EPWM7_SOCA
#define MTR2_ADC_I_SAMPLEWINDOW     14
#define MTR2_ADC_V_SAMPLEWINDOW     20

#define MTR2_IU_ADC_BASE        ADCA_BASE               // ADCA-A10*/C10
#define MTR2_IV_ADC_BASE        ADCC_BASE               // ADCC-A9/C8*
#define MTR2_IW_ADC_BASE        ADCC_BASE               // ADCC-A4/C14*
#define MTR2_VU_ADC_BASE        ADCA_BASE               // ADCA-A5*/C2
#define MTR2_VV_ADC_BASE        ADCA_BASE               // ADCC-A7*/C3
#define MTR2_VW_ADC_BASE        ADCC_BASE               // ADCA-A8/C11*
#define MTR2_VDC_ADC_BASE       ADCA_BASE               // ADCC-A1*

#define MTR2_IU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A10*/C10
#define MTR2_IV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A9/C8*
#define MTR2_IW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A4/C14*
#define MTR2_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A5*/C2
#define MTR2_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCC-A7*/C3
#define MTR2_VW_ADCRES_BASE     ADCCRESULT_BASE         // ADCA-A8/C11*
#define MTR2_VDC_ADCRES_BASE    ADCARESULT_BASE         // ADCC-A1*

#define MTR2_IU_ADC_CH_NUM      ADC_CH_ADCIN10          // ADCA-A10*/C10
#define MTR2_IV_ADC_CH_NUM      ADC_CH_ADCIN8          // ADCC-A9/C8*
#define MTR2_IW_ADC_CH_NUM      ADC_CH_ADCIN14           // ADCC-A4/C14*
#define MTR2_VU_ADC_CH_NUM      ADC_CH_ADCIN5           // ADCA-A5*/C2
#define MTR2_VV_ADC_CH_NUM      ADC_CH_ADCIN7           // ADCC-A7*/C3
#define MTR2_VW_ADC_CH_NUM      ADC_CH_ADCIN11           // ADCA-A8/C11*
#define MTR2_VDC_ADC_CH_NUM     ADC_CH_ADCIN1           // ADCC-A1*

#define MTR2_IU_ADC_SOC_NUM     ADC_SOC_NUMBER2         // ADCA-A10*/C10-SOC2-PPB2
#define MTR2_IV_ADC_SOC_NUM     ADC_SOC_NUMBER3         // ADCC-A9/C8* -SOC3-PPB3
#define MTR2_IW_ADC_SOC_NUM     ADC_SOC_NUMBER4         // ADCC-A4/C14* -SOC4-PPB4
#define MTR2_VU_ADC_SOC_NUM     ADC_SOC_NUMBER6         // ADCA-A5*/C2     -SOC6
#define MTR2_VV_ADC_SOC_NUM     ADC_SOC_NUMBER7         // ADCC-A7*/C3  -SOC7
#define MTR2_VW_ADC_SOC_NUM     ADC_SOC_NUMBER7         // ADCA-A8/C11*  -SOC7
#define MTR2_VDC_ADC_SOC_NUM    ADC_SOC_NUMBER8         // ADCC-A1*     -SOC8

#define MTR2_IU_ADC_PPB_NUM     ADC_PPB_NUMBER2         // ADCA-A10*/C10-SOC2-PPB2
#define MTR2_IV_ADC_PPB_NUM     ADC_PPB_NUMBER3         // ADCC-A9/C8* -SOC3-PPB3
#define MTR2_IW_ADC_PPB_NUM     ADC_PPB_NUMBER4         // ADCC-A4/C14*- SOC4-PPB4

// only for datalog and PWMDAC
#define MTR2_IU_ADCRESLT        MTR2_IU_ADCRES_BASE + ADC_O_RESULT2     // ADCA-A10*/C10-SOC2
#define MTR2_IV_ADCRESLT        MTR2_IV_ADCRES_BASE + ADC_O_RESULT3     // ADCC-A9/C8*  -SOC3
#define MTR2_IW_ADCRESLT        MTR2_IW_ADCRES_BASE + ADC_O_RESULT4     // ADCC-A4/C14* -SOC4

#define MTR2_VU_ADCRESLT        MTR2_VU_ADCRES_BASE + ADC_O_RESULT6     // ADCA-A5*/C2  -SOC6
#define MTR2_VV_ADCRESLT        MTR2_VV_ADCRES_BASE + ADC_O_RESULT7     // ADCC-A7*/C3  -SOC7
#define MTR2_VW_ADCRESLT        MTR2_VW_ADCRES_BASE + ADC_O_RESULT7     // ADCA-A8/C11* -SOC7
#define MTR2_VDC_ADCRESLT       MTR2_VDC_ADCRES_BASE + ADC_O_RESULT8    // ADCC-A1*     -SOC8

//------------------------------------------------------------------------------
// CMPSS
#define MTR2_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // CMPSS2-A10
#define MTR2_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_2    // CMPSS2-A10, N/A

#define MTR2_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // CMPSS2-C8
#define MTR2_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_2    // CMPSS2-C8

#define MTR2_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_4    // CMPSS2-C14, N/A
#define MTR2_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_4    // CMPSS2-C14

#define MTR2_IU_CMPHP_MUX       3                            // CMPSS2-A10
#define MTR2_IU_CMPLP_MUX       3                            // CMPSS2-A10

#define MTR2_IV_CMPHP_MUX       2                            // CMPSS2-C8
#define MTR2_IV_CMPLP_MUX       2                            // CMPSS2-C8

#define MTR2_IW_CMPHP_MUX       3                            // CMPSS2-C14
#define MTR2_IW_CMPLP_MUX       3                            // CMPSS2-C14

#define MTR2_CMPSS_DACH_VALUE   2048+1024+512
#define MTR2_CMPSS_DACL_VALUE   2048-1024-512

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR2_XBAR_TRIP_ADDRL    XBAR_O_TRIP5MUX0TO15CFG
#define MTR2_XBAR_TRIP_ADDRH    XBAR_O_TRIP5MUX16TO31CFG

#define MTR2_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX02_CMPSS2_CTRIPH       // CMPSS1-HP
#define MTR2_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX03_CMPSS2_CTRIPL  // CMPSS3-HP&LP
#define MTR2_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX06_CMPSS4_CTRIPH       // CMPSS1-LP

#define MTR2_IU_XBAR_MUX        XBAR_MUX02          // CMPSS1-HP
#define MTR2_IV_XBAR_MUX        XBAR_MUX03          // CMPSS3-HP&LP
#define MTR2_IW_XBAR_MUX        XBAR_MUX06          // CMPSS1-LP

#define MTR2_XBAR_INPUT1        XBAR_INPUT2
#define MTR2_TZ_OSHT1           EPWM_TZ_SIGNAL_OSHT2

#define MTR2_XBAR_TRIP          XBAR_TRIP5
#define MTR2_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN5

//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR2_PWM_DBFED_CNT      5           // 50ns

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR2_PWM_DBRED_CNT      5           // 50ns

Yanming Luo said:

Follow the lab user's guide to disconnect and reconnect some pins on LUANCHXL-F280025C and BOOSTXL-DRV8323RS.

I have followed the lab guide's BOOSTXL-DRV8323RS setup instructions for both.

You may try to run single motor on site-2 first to verify the hardware and configuration, and then run dual motor.

The motor 2 hardware seems to be functional, but I still can't do calcMotorOverCurrentThreshold() on motor 2 without causing the issue described above.

Check the flag of the EPWM and CMPSS status registers to see if there is any fault bits set, and make sure that the CMPSS and EWPM TZSEL registers are configured correctly as mentioned above.

Sasha Gold said:

The motor 2 hardware seems to be functional,

Did the motor run well on the site 2?

Hello Yanming,

As per provided code, registers should be configured an unique between motors.

The CMPSS status registers all appear to be ok:

Which is the EPWM status register? I looked through the technical manual and all I could find is TBSTS, which I don't think is correct?

The motor appears to run correctly on site 2.

Are there other things I could check?

Also since I'm using XBAR Trip7 and Trip 5 I believe it does not require setup of TZSEL? As mentioned previously, most of my code is directly from the the Universal Motor Control lab, which also does not use TZSEL as far as I can tell, unless SST_ENABLE is explicitly defined, which I am not using.

Not right. The TZSEL is still configured in HAL_setupMtrFaults() for nFault from DRV device and the output from CMPSS.

Attached files for your reference, the project can run dual motor verified on LUANCHXL-F280025C and 2 * BOOSTXL-DRV8323RH. The project uses the similar architecture as universal lab.

1856.hal.c6116.hal.h

Hi Yanming,

Correction, I do set input x bar trip zone for both motors for nFault, I thought you were referring to something else as it is not referred to as TZSEL in that case. I assume you mean this within HAL_setupMtrFaults():

// configure the input x bar for TZ2 to GPIO, where Over Current is connected
XBAR_setInputPin(INPUTXBAR_BASE, MTR2_XBAR_INPUT1, MTR2_PM_nFAULT_GPIO);
XBAR_lockInput(INPUTXBAR_BASE, MTR2_XBAR_INPUT1);

I compared my code with yours and found a few differences:

• My MTR1_GATE_EN_GPIO was set to 29, yours is 28.
• My HAL_enablePWM and HAL_clrMtrFaultStatus functions did not specifically clear the high or low latches based on hal settings, they just cleared filter latches high and low for each cmpssHandle
• The ADC setup was different, but as far as I can tell both should work (i.e. where A3 and C5 are both valid, I had been using A3 where you are using C5)
• My MTR2_GATE_CAL_GPIO was 27, you had 46. How did you get this number?
• For motor 2, I was using Trip 5 where you are using Trip 8

I tried changing all of these to follow your version's code but it does not seem to make any difference. The issue still occurs and speed control is not working. Does your project use calcMotorOverCurrentThreshold() on both motors in the main control loop?

I still have not found the EPWM status register you had mentioned previously, do you know the specific register name?

I found where GPIO 46 came from, that was my mistake I clearly made a copy paste error.

Looking closer at your example project, I found that the CMPHP and CMPLP are not unique. i.e. both M1 IW and M2 IU use HPMXSEL 3 and both M2 IV and M2 IW use HMPXSEL 0. Do these not have to be unique? I found while debugging that the AnalogSubsysRegs.CMPHPMXSEL and AnalogSubsysRegs.CMPLPMXSEL registers would get written to twice in some cases, overwriting the first setting.

Use the same CMPSS, but different input channel for each phase. If not enough channel, have to only use two inputs for three phase as did in the example. Just as an example to simplify the configuration, the first one is useless that will be ignored. You should change the configuration according to your hardware board.

I am now using 2 comparators per motor, therefore only monitoring 4 of the 6 current phases.

My initial issue remains, the calcMotorOverCurrentThreshold() continues to cause strange control behaviour. I may simply remove this code as written by TI. It's not a true resolution but I can't seem to fix it.

You need to change the ADC, CMPSS and EPWM configuration functions according to the hardware. Check the control and status registers of the related CMPSS and EPWM to know which fault flag is set, and then you can check if the configuration codes are correct in HAL_setupCMPSSs() and HAL_setupMtrFaults().

Also, you need to change the code in HAL_setMtrCMPSSDACValue() according to the using CMPSS for each motor.

The code I shared with you is based on the Rev. 1 LaunchXL-F280025C that has a little bit difference on GPIO assignment to the formal LaunchXL-F280025C you have. It's just for your reference, not a solution for you.

Hi Yanming, thanks for your continued support.

As mentioned in my original question, I have made changes to the ADC, CMPSS, and ePWM configurations, specifically by making changes to the following functions provided by the universal lab:

Sasha Gold said:

HAL_setupADCs, HAL_setupCMPSSs, HAL_setupMtrFaults, HAL_setupPWMs

I did miss HAL_setMtrCMPSSDACValue, thanks for catching that. I've fixed it now.

I'm still seeing the issue unfortunately.