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TMS320F280039C: Accurate timing from triggering to Sample and Hold

Wayne Huang
Genius 16925 points

Part Number: TMS320F280039C

Dear Champs,

I am asking this for our customer.

The user wonders accurate timing in SYSCLK from triggering to S+H (sample and hold) for digital power control.

1. For example, if the user uses PWM1 to generate SOCA at PWM1 counter = 0 to trigger ADCA1 SOC0, then when does SOC0 start? Let PWM1 counter = N to show the SYSCLK cycle that SOC0 starts S+H, how to calculate N? Would you please give a detail estimation here?

2. From below ADC timing from the TRM, is this ADCTRIG just means PWMSOCA above if it's triggered by PWMSOCA?

Is the delay in red below fixed in 2 SYSCLK cycle or variable?

3. From 16.8.4 PPB Sample Delay Capture of the TRM, does that mean there is a DLYSTAMP SYSCLK cycles in between ADCSOCFLG.SOC0 and the real start of S+H? Is there any further timing to show DLYSTAMP?We are confused about using DLYSTAMP. 

Wayne Huang

  • +1
    TI__Guru 60865 points

    Hi Wayne,

    The 2 SYSCLK cycle delay shown in the timing diagram is the correct amount between ePWM compare, zero, or period match and the S+H from the first SOC starting and this is a fixed delay.  If the first SOC is SOC0 and the next SOC pending is SOC1, then SOC1 S+H will start (2 + tSH of SOC0 + teoc) SYSCLK cycles after the ePWM trigger.

    Yes, ADCTRIG is whatever trigger source is used.  This could be ePWM compare, zero, or period match or something else like CPUTIMER pulse or even software trigger. 

    The delay stamp captures the time between the SOC flag being set and the S+H starting, so if SOC0 is triggered directly and doesn't have to wait, I believe the delay stamp will read 2 cycles.  Subsequent SOCs in a sequence of conversions will read larger values as mentioned above because the SOC pending flag is set when the trigger occurs, but the SOCs will convert sequentially.  The main use case for this feature is to detect if a given SOC is delayed vs. expected baseline time between SOC flag being set and the SOC starting.  The most likely cause of this would be running multiple async. sets of conversions through the same ADC.   So for instance, if an SOC is the first in a set of conversions but the delay stamp reads a value > 2, then the SOC was delayed.