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TMS320F28386D: CPU1 reads CPU2_to_CPU1 MSGRAM0 when CPU2 is held in reset.

Part Number: TMS320F28386D

Hi champs,

My customer develops his project by using CCS debug mode without problems, but he finds that F28386D fails to boot-up when standalone flash boot.

I find that the CPU1 tries to read CPU2_to_CPU1 MSGRAM0 when CPU2 is held in reset and then CPU1 is stuck, I suggest my customer modifies the code, deactivate CPU2 reset before reading that MSGRAM0 and this problem is fixed.

My question is that what will happen if CPU1 reads CPU2_to_CPU1 MSGRAMx while CPU2 is held in reset, will CPU1 be stuck?



  • Luke,

    Did the customer check where CPU1 code is stuck? I wondering whether CPU1 code is expecting a specific value from CPU2 MSGRAM and hence stuck in infinite loop



  • Manoj,

    The code is simple if/else C statements as below,

    if(variable.bit) {
         // do task1 here
    else {
         // do task2 here

    The variable is defined in CPU2_to_CPU1 MSGRAM0, CPU1 is stuck when execute if(variable.bit) statement, the strange thing is that CPU1 is not always stuck, only around 50% chance, means that if we restart system 10 times, CPU1 could stuck 5 times. When this problem happen, the XRSn pin will output a low pulse around 50us per 81ms, we are sure the watchdog timer is disabled, so this is not the watchdog timer reset.

    Can CPU1 read CPU2_to_CPU1 MSGRAMx when CPU2 is held in reset?



  • Can CPU1 read CPU2_to_CPU1 MSGRAMx when CPU2 is held in reset?

    CPU2 MSGRAM runs out of CPU2.SYSCLK. Any reads to CPU2.MSGRAM  doesn't make sense because CPU2 is still held in reset. So, it is an invalid access. Design team will anyway say you shouldn't access MSGRAM when CPU2 is still held in reset. So, we might just have additional information which may not be useful to customer and it may not be of any value. If you really need it I shall check with design what would the result of MSGRAM reads. But, this would take atleast 2 weeks to hear back from them.