TMS320F28388D: IPC register atomic

Vi Phan1

Prodigy 40 points

Part Number: TMS320F28388D

Hello

I have some questions regarding to whether the ipc registers between cm and cpu1 are atomic.

I tried to send data from CM core to CPU1 core by using ipc register that is:

- CPU1 read data from CMTOCPUxIPCRECVADDR register.

- CM write data to CMTOCPUxIPCSENDADDR register.

Most of the time, I'm able to get the correct data sent from CM to CPU1, but there's some occasion that CPU1 read some incorrect data, and after reading the register again, it reads the correct data.

Example from the scenario is like

CM write 256 to CMTOCPUxIPCSENDADDR register

CPU1 read from CMTOCPUxIPCRECVADDR register, get some random value (it seems random and has no pattern to it)

CPU1 read from CMTOCPUxIPCRECVADDR register again, get the correct value of 256.

I also saw something like that happened in other communication CPU1 -> CM

Not sure if it's the case that when CM and CPU1 try to access the register at the same, and if register is not atomic, data doesn't completely change to correct value.

Please let me know if you find out anything about this problem

Thanks

over 4 years ago

0 Manoj Santha Mohan over 4 years ago

TI__Guru 55700 points

Are you using IPC_sendCommand and IPC_readCommand to achieve the above operation?

1) Only after you write to IPC_SENDCOM, IPC_SENDDATA, IPC_SENDADDR and then set IPC flag from CM side.

2) From CPU1 side, make sure corresponding IPC flag is set from CPU1 side and then read IPC_RECVCOM, IPC_RECVDATA, IPC_RECVADDR

The key is you shouldn't read IPC_RECVCOM, IPC_RECVDATA, IPC_RECVADDR unless corresponding IPC flag is set. Unless you do this, you cannot do CPU1 reads. If you do it may have incorrect data.

Regards,

Manoj

0 Vi Phan1 over 4 years ago in reply to Manoj Santha Mohan

Prodigy 40 points

Thanks for your response

I'm not using any example code from TI.

I know that setting and checking IPC flag will help with this problem, but I want to have more understanding on this problem. Is there any document on inter-process communication spec or something like if the registers are atomic, how long I need to delay for data to be valid when sending from 1 core to other.

0 Manoj Santha Mohan over 4 years ago in reply to Vi Phan1

TI__Guru 55700 points

What do you mean when you say the registers are atomic?

0 Vi Phan1 over 4 years ago in reply to Manoj Santha Mohan

Prodigy 40 points

What I mean is that CPU1 should either read the correct ready value or the old value rather than reading some random value from ipc registers while value is in process of changing.

0 Manoj Santha Mohan over 4 years ago in reply to Vi Phan1

TI__Guru 55700 points

These registers aren't atomic. You cannot read IPC_RECVCOM, IPC_RECVDATA, IPC_RECVADDR unless corresponding IPC flag is set (from remote CPU) as I had mentioned in above post.

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TMS320F28388D: IPC register atomic