TMS320F280041: dv/dt rate limit for AIOs

Koichiro Tashiro

Part Number: TMS320F280041

Hi,

I have a question from my customer about below datasheet description.
In datasheet section 6.4.2, there is a Note.
https://www.ti.com/lit/ds/symlink/tms320f280041.pdf?ts=1646719408302&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTMS320F280041

Question:
Q1) What the "high dv/dt" exactly means? Do we have any guideline to limit the edge rate?
Q2) If analog function is not used by adjacent signals, customer does not need to care about dv/dt rate?

Thanks and regards,
Koichiro Tashiro

over 2 years ago

+1 Frank Ankapong over 2 years ago

TI__Mastermind 28275 points

Hi Koichiro,

Koichiro Tashiro said:
Q1) What the "high dv/dt" exactly means? Do we have any guideline to limit the edge rate?

We do not have bounds for this since the different analog modules on the device have different sensitivities. Nevertheless for example, if your signal is 1MHz, there is really no need for the edge rate to be < 5ns. Practically speaking, only the ADC will experience some coupling since it's more sensitive. The other analog modules like PGA, DAC, CMPSS are fairly immune. You can limit the edge rate using some small capacitance.

Koichiro Tashiro said:
Q2) If analog function is not used by adjacent signals, customer does not need to care about dv/dt rate?

Correct.

0 Koichiro Tashiro over 2 years ago in reply to Frank Ankapong

TI__Mastermind 21140 points

Hi Frank,

Thanks for your quick reply!

Thanks and regards,
Koichiro Tashiro

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F280041: dv/dt rate limit for AIOs