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TMDSCNCD280049C: GPIO_setQualificationPeriod function

Part Number: TMDSCNCD280049C

Dear Sirs

I'm trying to understand the interrupt functions, capabilities and timing of the F28004x uC.  I'm using the "interrupt_ex1_external" example project to do this.  In my efforts to understand what is going on in the program, I fail to understand what the GPIO_setQualificationPeriod() function is for.  At first it looks like some sort of de-bounce type of function.  I read the function description.  The divider parameter description says it's  the output drive strength but then it says it's the value by which the frequency of the SYSCLKOUT is divided, which sounds like it's a time delay parameter.  Please clarify.  What does the function do to the GPIO pins?  

  • Hi,

    The TRM section "Input qualification" under GPIO chapter talks more about this. Did you get a chance to look at it?

    Regards,

    Veena

  • Dear Veena

    In an effort to understand the DEVICE_DELAY_US()  macro, I've altered one of the example programs.  Please see snippet. 

    //
    // Set GPIO16
    //
    GPIO_writePin(16, 1);

    //
    // Wait for Qual period
    //
    DEVICE_DELAY_US(DELAY);

    //
    // ReSet GPIO16
    //
    GPIO_writePin(16, 0);

    DELAY is defined as 

    // Qualification period at 6 samples in microseconds
    #define DELAY             (6.0 * 510.0 * 1000000.0 * (1.0 / DEVICE_SYSCLK_FREQ))

    I calculate DELAY = 30.6.  This should lead to a delay of 30.6us.  However, when I observed the GPIO16 pin with the scope, I see 560ns of delay.  Please explain.  Thank you.  

    DEVICE_SYSCLK_FREQ is defined as (in device.h)

    //*****************************************************************************
    //
    // Defines related to clock configuration
    //
    //*****************************************************************************
    //
    // 20MHz XTAL on controlCARD and Launchpad. For use with SysCtl_getClock().
    //
    #define DEVICE_OSCSRC_FREQ             20000000U

    //
    // Define to pass to SysCtl_setClock(). Will configure the clock as follows:
    // PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
    //
    #define DEVICE_SETCLOCK_CFG             (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | \
                                                                           SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
                                                                           SYSCTL_PLL_ENABLE)

    //
    // 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
    // code below if a different clock configuration is used!
    //
    #define DEVICE_SYSCLK_FREQ               ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2)

    //
    // 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
    // low speed peripheral clock divider of 4. Update the code below if a
    // different LSPCLK divider is used!
    //
    #define DEVICE_LSPCLK_FREQ                 (DEVICE_SYSCLK_FREQ / 4)

     The DEVICE_DELAY_US()  macro is defined as (in device.h)

    //*****************************************************************************
    //
    // Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
    // will convert the desired delay in microseconds to the count value expected
    // by the function. \b x is the number of microseconds to delay.
    //
    //*****************************************************************************
    #define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
    (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)

  • Dear Veena

    I'm very sorry for the trouble.  Please except my apologies.  I found my error using the scope and all is working as expected.  This resolves this issue.  Thank you for your help.