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Violating XINTF wait state requirements!

Janek Olszak
Prodigy 100 points

Hi! 

I'm connecting an adc to XINTF. Don't want to use any of the xinf signals, just want the DMA to take the data from the bus. 

  1. Can I violate the minimum wait state requirements for Lead and Active period in read cycle? 
  2. When is the data latched during the read cycle?

I use C28346 and ADS62P42

thanks,

Janek

  • 0
    TI__Guru* 89465 points

    Janek Olszak said:

    I'm connecting an adc to XINTF. Don't want to use any of the xinf signals, just want the DMA to take the data from the bus. 

    1. Can I violate the minimum wait state requirements for Lead and Active period in read cycle? 

    The XINTF is strobe based - this means it will sample relative to the strobes even if the external device doesn't use the strobes.

    Janek Olszak said:
    When is the data latched during the read cycle?

    Refer to the data manual.  For the 28346 this is www.ti.com/lit/SPRS516 refer to Table 6-37. External Interface Read Timing Requirements.  The important parameters are ta(A) and ta(RD). 

    Regards,

    Lori

     

     

     

  • 0 in reply to Lori Heustess
    Prodigy 100 points

    Lori Heustess said:

    I'm connecting an adc to XINTF. Don't want to use any of the xinf signals, just want the DMA to take the data from the bus. 

    1. Can I violate the minimum wait state requirements for Lead and Active period in read cycle? 

    The XINTF is strobe based - this means it will sample relative to the strobes even if the external device doesn't use the strobes.

    [/quote]

    Sory, my question was about number of XTIMCLK cycles during Lead and Active period. The manual states that Lead period needs to be at least 2 cycles long and Active 6 cycles long. Your answer here suggests that those periods can be reduced but won't work in every temperature.

    Lori Heustess said:

    When is the data latched during the read cycle?

    Refer to the data manual.  For the 28346 this is www.ti.com/lit/SPRS516 refer to Table 6-37. External Interface Read Timing Requirements.  The important parameters are ta(A) and ta(RD). 

    Regards,

    Lori

    [/quote]

    According to this table data latch will happen after (LR + AR) – 13.5ns . But what if one is using XREADY? Data is latched on the last XTIMCLK cycle in the actice period, right?

     

     

     

     

     

  • 0 in reply to Janek Olszak
    TI__Guru* 89465 points

    Janek Olszak said:

    Sory, my question was about number of XTIMCLK cycles during Lead and Active period. The manual states that Lead period needs to be at least 2 cycles long and Active 6 cycles long. Your answer here suggests that those periods can be reduced but won't work in every temperature.

    The Lead + Active time determine when the data is sampled.  This is what I meant by it is strobe based, not clock based.   If the requirements are not followed then, yes, it is likely not to work on every device at every temp within the voltage limits of the device.  

    Janek Olszak said:

    According to this table data latch will happen after (LR + AR) – 13.5ns . But what if one is using XREADY? Data is latched on the last XTIMCLK cycle in the actice period, right?

    Yes, you are correct.  XREADY will extend the active period.  Once XREADY is detected as high, the active period will complete as normal and the data will be latched.  I see in the data manual this is not clear by the ta(A) value for XREADY.  I will feed this back to the team.

    Regards,

    Lori