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TMS320F280049: F280049 missing clock question

Huihuang Chen
Expert 3830 points
Part Number: TMS320F280049

Hi Champ,

I know after a missing clock condition be detected the CPUCLK will become INTOSC1.

I want to know during the OSCCLK missing to a missing clock condition be detected, what is the frequency of CPUCLK?

  • 0
    TI__Guru 71785 points

    Huihuang,

    It will be unknown during that time.  Until the 13-bit MCDSCNT counter clocked from INTSOC1 overflows the clock source will remain unchanged. 

    So worst case there would be 819.2us(based on 10MHz INTOSC1) when the device is running either at very slow clock or not clocked at all.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 3830 points

    Hi Matt,

    Could you advise the detail why it is unknown, customer want to know the detail, as it is important for the system production.

    if not clocked during this time? the CMPSS still work or not? as 819.2us is too long time, if CMPSS not working during this time, the OVP/OCP protection will be failed, some system will be damaged.

  • 0 in reply to Huihuang Chen
    TI__Guru 71785 points

    Huihuang,

    Thanks for the additional detail.  The CMPSS is purely analog block and the trip functions can function properly without a system clock, so system should be safe during this time before missing clock is detected.  I will double check this detail and reply back to the E2E.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 3830 points

    Hi Matt,

    For CMPSS , if customer use filter output, the CMPSS output maybe have issue, be help to confirm.

    Thanks!

  • 0 in reply to Huihuang Chen
    TI__Guru 71785 points

    Huihuang,

    You are correct, if customer uses any path but ASYNC then the clock will be in play and effect the signal. 

    However, I forgot to add one detail to my previous statement, and that is the PLL.  Assuming customer is using PLL and not just the straight XCLKIN, then if external clock goes missing the PLL will operate at its limp mode frequency,in the 100Hz range.  This will allow those paths that need a clock to continue to propagate, just at a much slower rate.

    If customer is not using the PLL, then my earlier statement holds that there will not be a clock until the switch over.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 3830 points

    Hi Matt,

    Sorry , can you explain the detail of ASYNC then the clock will be in play and effect the signal, if customer used digital filter , during this time  the CMPSS output will be  affect or not?

    Can you confirm during the OSCCLK missing to a missing clock condition be detected, the  PLL will operate at  its limp mode frequency, in the 100Hz range?

    For "the  PLL will operate at  its limp mode frequency", it is no mentioned in TRM, Are you sure it is 100Hz? or it is in some range?

  • 0 in reply to Huihuang Chen
    TI__Guru 71785 points

    Huihuang,

    Since the digital filters use the CPU clock to qualify the comparator output, if there is no clock at all the digital filter will not change state in this condition.  Only the ASYNC path is direct to the trip logic in the PWM and will work in absence of clocks.

    I'm still looking into the last question with some others in the C2000 team.  Please give me an additional day to reply.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    TI__Guru 71785 points

    Huihuang,

    I have more clarification here, the PLL limp frequency will be in the 100 of kHz(not Hz).  So when clock goes missing with PLL active the output will begin to slow toward this frequency.  Eventually the missing clock detect will still trip and reset the device(if so configured).

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 3830 points

    Hi Matt,

    Thanks a lot for your kindly support!

    The output will begin to slow toward this frequency, that means the PLL clock will start at 100KHz and  slow down ? if so , any range about this frequency range like from 100KHz to slow down to which frequency? how about the deceleration ?

  • 0 in reply to Huihuang Chen
    TI__Guru 71785 points

    From my understanding the output will be at the normal operating frequency before the clock goes missing, then decay down to the 100kHz level.  So we would decay from 100MHz operation to this value.  I think there are variables like device temp/voltage that may effect this decay somewhat, but I do not have an reference data to share on any typical behavior.

    Best,

    Matthew