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TMS320F280045: Total current draw

Part Number: TMS320F280045
Other Parts Discussed in Thread: TMDSHSECDOCK

Dear Sirs

Please see attached schematic.  I've just received the boards from the board assembler and tried to power on up.  The power supply got blisteringly hot and the TMS320F280045RSHSR uC got very warm.  I measured the input current and saw it was 900mA.  I inspected the board very closely for assembly errors and found none.  I reviewed my design and found a couple of things wrong.  First, VDDIO_SW (pin 48) was not connected to VDDIO.  That has been corrected with a jumper wire.  The second issue is GPIO22_VFBSW (pin 51) is connected to an output pin.  This should be no problem as it is not connected to anything at this time.  I took another board and made the corrections and still have the same problem.  If it is possible, please do a peer review on my design and inform me of any issues you see.  I'm using the TMS3230F280049C control card and the TMDSHSECDOCK docking station for code development.  I measured the input current of this board set and it was less than 50mA.  It's obvious that I've done something wrong here.  Any help will be sincerely appreciated.  Thank you.

10mm_Top-Hat_Alternate schematic 1-19-2022.pdf

  • Hi Dennis,

    I'd suggest you review the Hardware guide app note for proper C2000 PCB design practices, Also this excel checklist may help you identify something quickly, Checking your board for solder shorts would be good too.

    If we review and find something notable in your sch we'll let you know.



  • Kevin

    thank you for you timely response.  I will do as you suggested.  However, I believe I've found the problem.  If you look at the first page of the schematic, you will note that I tied +3.3vdc to VDD.  If I'm correct, this is absolutely wrong.  Am I correct on this?  

  • Hi Dennis,

    Below are the observations in the schematic:

    1. VDDIO_SW (pin 48) was not connected to VDDIO. It should be connected (pointed by customer)

    2. JTAG_TMS - recommended pull-up resistor 2.2kOhms as of DS

    3. I would recommend using ferrite beads to separate +3.3V (from LDO) with 3.3VDDA and also 3.3V with 3.3VDDIO. The usage can be seen in F280049C control card schematics in - Incase if you plan for a redesign

    4. As you pointed 3.3V tied to VDD (which is 1.2V) in your schematic is not seen. VDD for this device only internal VREG (1.2V) is feasible but not 3.3V 

    5. Next on the layout follow PCB design practices shared by Kevin. From my understanding the high current drawn is because - if there is no proper Analog GND and Digital GND separation.

    Let us know you have further queries. 




  • Dear Uttam

    Thank you for you observations and suggestions.  Yes, there will be a redesign required.  As to the +3.3V being tied to the VDD, can I assume that the uC is now destroyed?  

  • Hi Dennis, 

    As per DS the maximum VDD voltage which can be applied is 1.5V. So Yes, device might be destroyed. Its a good practice to use new one.